              S6J3360/S6J3370 series I/O register file manual  version 1.0

                                              Cypress Semiconductor Corporation


1.Preface
   "S6J3360/S6J3370 series I/O register file" (The I/O register file) provides symbols 
   (C language macro) to access the peripheral registers(I/O registers) of
   S6J3360/S6J3370 series and the bits of the I/O register.

2.How to use
  Please include s6j3360io.h by user program. s6j3360io.h is stored at 
  "s6j3360ioh_<version>\include". <version> means package version of the I/O
  register file (example: V01L01).
  
  - NOTE -
    - Standard C include file stdint.h is needed in the I/O register file.
      If your compiler does not have stdint.h, please make stdint.h in the
      following contents.

        typedef unsigned long   uint32_t;
        typedef unsigned short  uint16_t;
        typedef unsigned char   uint8_t;

3.Kinds of macros
  The table below shows the macro of the I/O register file.

  Table 3-1 Kinds of macros
  --------------------------------------------------------------------
  Kinds of macros    description
  --------------------------------------------------------------------
  register macro     Macro to access each I/O register.
  bit macro          Macro to access each bit in I/O register.
  --------------------------------------------------------------------

  - The register macros and the bit macros are individually prepared each I/O
    register and each bit.

  - There are also macros that access adjoining two or more I/O registers or
    bits at the same time because of the restriction of the access size in the
    hardware specifications or the convenience on user programming.

  - The access size of bit macro depends on the compiler. Therefore bit macro
    of the I/O register of which the access size is restricted is provided
    only if the bit(s) of the I/O register match the following condition.
    For example, in the case of the I/O register which is permitted only word
    access (byte access and halfword access are not permitted), bit macro is
    provided to only the bit field of 17 bits or more.

      Bit width of bit field > Maximum prohibition access size

  - The access macro for write-only bit which must be written with other bit of
    the same I/O register simultaneously is not provided.

  - The substance of the register macros and the bit macros are the reference
    by pointer to the peripheral area.
    Please refer to "5. The substance of macros" for details.

  - The macro of the register where floating type's data is stored is defined
    by the floating type, but other macros are defined by the unsigned integer
    type. Therefore the type conversion(cast) from unsigned integer to signed
    integer which is as follows is necessary for the I/O register of which the
    type is signed integer.

    Example)
        #define READasS16(reg)         ( *(signed short*)(&(reg)) )
 
        signed short  agvl;
 
        /* MVA00_MVAAGVL is read as 16bit signed integer. */
        agvl = READasS16(MVA00_MVAAGVL);

4.Macro name rules
  The macros are named according to following naming rule 1 to 3.

  <Naming rule 1>
  The macros individually prepared for each I/O register and each bit are
  named as follows.

    Register macros : <peripheral identifier>_<register name>
    Bit macros      : <peripheral identifier>_<register name>_<bit name>

        <peripheral identifier> : Abbreviation of peripheral and channel
                                  (or unit) number. 
        <register name>         : Register name described in the hardware
                                  mannual.
        <bit name>              : bit(s) name described in the hardware mannual

    Example) SMR register of the 2nd channel of UART(Multi Function Serial
             interface)  

             MFS02_UART_SMR

    Notes
      Some I/O register names include "Peripheral identifier _" on the
      hardware specifications.
      In this case, "Peripheral identifier _" is not added to the macro name.

  <Naming rule 2>
  A common part of the name of the I/O registers is used as follows [1][2] for
  the macro which accesses two or more adjoining I/O registers simultaneously.
  The naming rule of the bit macro which accesses two or more bits
  simultaneously is identical with the above rules (rule [3]).

    Example)
      [1]If the register name is REG3, and REG4 : PE_REG
      [2]If the register name is RGH, and RGL   : PE_RG
      [3]If the bits are BT0-BT3 in REG registers : PE_REG_BT

      (*) PE is a peripheral identifier.

  <Naming rule 3>
  If naming rule 2 cannot be applied (e.g. duplication of the name), the I/O
  register names are integrated as follows [1][2]. The bit numbers are
  concatenated by "_" for the bit name as follows [3].

    Example)
      [1]If the object register name is REG3, and REG4 : PE_REG43
      [2]If the object register name is RGH, and RGL   : PE_RGHL
      [3]If the object bit name is BT0-BT3 in REG registers : PE_REG_BT3_0

      (*) PE is a peripheral identifier.

  <Special case 1>
  If the accessible size of the register is smaller than the size of the target
  register, the following character string is added to the end of the register
  name.

  - If the size of the target register is 2byte
    +-----------------+-----------------+
    |                 |    Offset       |
    | Access size of  +-----------------+
    | macro           |   +0   |   +1   |
    +-----------------+-----------------+
    | 1Byte           |   _0   |   _1   |
    +-----------------+-----------------+

  - If the size of the target register is 4byte
    +-----------------+-----------------------------------+
    |                 |             Offset                |
    | Access size of  +-----------------------------------+
    | macro           |   +0   |   +1   |   +2   |   +3   |
    +-----------------+-----------------------------------+
    | 2Byte           |       _L        |       _H        |
    +-----------------+-----------------------------------+
    | 1Byte           |   _0   |   _1   |   _2   |   _3   |
    +-----------------+-----------------------------------+

  - If the size of the target register is 8byte
    +-----------------+-----------------------------------------------------------------------+
    |                 |                               Offset                                  |
    | Access size of  +-----------------------------------------------------------------------+
    | macro           |   +0   |   +1   |   +2   |   +3   |   +4   |   +5   |   +6   |   +7   |
    +-----------------+-----------------------------------------------------------------------+
    | 4Byte           |                _L                 |                _H                 |
    +-----------------+-----------------------------------------------------------------------+
    | 2Byte           |      _HW0       |      _HW1       |      _HW2       |      _HW3       |
    +-----------------+-----------------------------------------------------------------------+
    | 1Byte           |   _0   |   _1   |   _2   |   _3   |   _4   |   _5   |   _6   |   _7   |
    +-----------------+-----------------------------------------------------------------------+

  - If the size of the target register is bigger than 8byte
    +-----------------+-----------------------------------+
    |                 |             Offset                |
    | Access size of  +-----------------------------------+
    | macro           |  +0*S  |  +1*S  |  ...   |  +n*S  |
    +-----------------+-----------------------------------+
    | 8Byte           |  _DW0  |  _DW1  |  ...   |  _DWn  |
    +-----------------+-----------------------------------+
    | 4Byte           |   _W0  |   _W1  |  ...   |   _Wn  |
    +-----------------+-----------------------------------+
    | 2Byte           |  _HW0  |  _HW1  |  ...   |  _HWn  |
    +-----------------+-----------------------------------+
    | 1Byte           |    _0  |    _1  |  ...   |    _n  |
    +-----------------+-----------------------------------+
    (*) S is the access size of macro

    Example) If the size of the target register is 4byte, the accessible size
             is 1byte, and register name is RG :
    
       [1] Offset(+0) : PE_RG_0
       [2] Offset(+1) : PE_RG_1
       [3] Offset(+2) : PE_RG_2
       [4] Offset(+3) : PE_RG_3

      (*) PE is peripheral identifier

  <Special case 2>
  If on the hardware specifications there are several different peripheral 
  identifiers that are not located in order in a peripheral, the same 
  peripheral identifier is used for macro names as follows [1][2].

    Examplej
      [1]A part of registers has different peripheral identifier from the 
         other registers. 

          Offset     Register  Peripheral identifier  Macro name
          0x0000     REG1      PE_A                   PE_A_REG1
          0x0004     REG2      PE_A                   PE_A_REG2
          0x0008     REG3      PE_B                   PE_A_REG3
          0x000C     REG4      PE_A                   PE_A_REG4
          0x0010     REG5      PE_A                   PE_A_REG5
          0x0014     REG6      PE_A                   PE_A_REG6

      [2]Registers have several different peripheral identifiers that are not 
         located in order.

          Offset     Register  Peripheral identifier  Macro name
          0x0000     REG1      PE_A                   PE_X_REG1
          0x0004     REG2      PE_A                   PE_X_REG2
          0x0008     REG3      PE_B                   PE_X_REG3
          0x000C     REG4      PE_C                   PE_X_REG4
          0x0010     REG5      PE_B                   PE_X_REG5
          0x0014     REG6      PE_C                   PE_X_REG6

5.The substance of macros
  - The substance of the register macros and the bit macros are the reference
    by pointer to the peripheral area as follows.

      *((volatile typePERI*)base_addr).REG_member.int_member
      *((volatile typePERI*)base_addr).REG_member.stc_member.bit_member

         typePERI   : Structure data type of peripherals
         base_addr  : Base addresses of peripherals (each channel/unit)
         REG_member : Member of union data means I/O registers
         int_member : Integer member of bit length of I/O registers
         bit_member : Bit field member means bits of I/O registers

  - The bit macros for bit accessible via Bit Band Alias area refer to the
    corresponding address of Bit Band Alias area in the following form not
    above-mentioned.

      *((volatile uint8_t*)0xa0000000+offset)

6.Macro name

6.1 Macro name list
  The concrete macro names of each I/O register and each bit are described in
  the macro name list file of each peripheral shown in the table below.
  Macro name list files are stored at "s6j3360ioh_<version>\symbol_list".

  Table 6-1 Macro name list
  ----------------------------------------------------------------------------
  Macro name list file   Target peripheral
  ----------------------------------------------------------------------------
  ADC12B.sym.txt            12/10/8bit Analog to Digital Converter
  BTSEL.sym.txt             Base Timer I/O Selection Function
  BT_PPG.sym.txt            Base Timer (PPG timer)
  BT_PWC.sym.txt            Base Timer (PWC timer)
  BT_PWM.sym.txt            Base Timer (PWM timer)
  BT_RT.sym.txt             Base Timer (Reload Timer)
  CANFD.sym.txt             CAN FD Controller(MCAN3.2)
  CANP.sym.txt              CAN Prescaler
  CM.sym.txt                Clock Monitor
  CRC.sym.txt               CRC
  CU.sym.txt                CR calibration
  DDRHSSPI.sym.txt          DDR High Speed SPI Controller
  DMA.sym.txt               DMA Controller
  DMAA.sym.txt              DMA COMPLEX SUBSYSTEM
  EBI.sym.txt               External Bus Interface
  EIC.sym.txt               External Interrupt
  EP.sym.txt                EXPAND PLL
  EXCFG.sym.txt             BootROM Hardware Interface
  FRT.sym.txt               32bit Free-Run Timer
  GPIO.sym.txt              I/O Port (GPIO)
  GT.sym.txt                Base Timer Simultaneous Operation (GT)
  HWDG.sym.txt              Hardware WatchDog Timer
  I2S.sym.txt               Inter IC Sound(I2S)
  ICU.sym.txt               32bit Input Capture
  INDPWM.sym.txt            Indicator PWM
  IRC.sym.txt               Interrupt Controller
  LCDB.sym.txt              LCD Bus Interface(LCDBusIF)
  LCDC.sym.txt              LCD Controller(LCDC)
  LCDE.sym.txt              LCD Controller(LCDE)
  MCG.sym.txt               Low Power Consumption(MCG)
  MFS_CSIO.sym.txt          Multi Function Serial Interface (CSIO)
  MFS_I2C.sym.txt           Multi Function Serial Interface (I2C)
  MFS_LIN.sym.txt           Multi Function Serial Interface (LIN)
  MFS_UART.sym.txt          Multi Function Serial Interface (UART)
  MODEC.sym.txt             Operation Mode
  MPUH.sym.txt              MPU16 AHB
  MPUX.sym.txt              Memory Protection Unit for AXI
  OCU.sym.txt               32bit Output Compare
  PCMPWM.sym.txt            PCM-PWM
  PPC.sym.txt               I/O Port (PPC)
  PPU.sym.txt               Peripheral Protection Unit
  PRGCRC.sym.txt            Programmable CRC
  PWU.sym.txt               Partial Wakeup Control
  QC.sym.txt                Quad Position & Revolution Counter
  RIC.sym.txt               I/O Port (RIC)
  RLT.sym.txt               32-bit Reload Timer
  RTC.sym.txt               Real Time Clock
  SG.sym.txt                Sound Generator
  SHE.sym.txt               Secure Hardware Extension
                            Memory Protection Unit for AXI of SHE
  SMC.sym.txt               Stepper Motor Controller
  SMCTG.sym.txt             Trigger Configuration Of Stepper Motor Controller
  SMIX.sym.txt              Sound Mixer
  SRCFG.sym.txt             System SRAM Module(SRAM_IF)
  SWDG.sym.txt              Software WatchDog Timer
  SWFG.sym.txt              Sound Waveform Generator
  SYSC.sym.txt              Reset
                            Clock System
                            Low Power Consumption
                            Clock Supervisor
                            Source Clock Timer
  TCFCFG.sym.txt            TCFLASH
  TPU.sym.txt               Time Protection
  TRCFG.sym.txt             TCRAM Interface
  WFCFG.sym.txt             WorkFLASH
  ----------------------------------------------------------------------------

6.2 Description form
  Each file of the macro lists is described in the form of the following. 
  However, <<Reserved symbol>> is a reservation macro defined so that the
  I/O register file may internally use it.

  <<Reserved symbol>>
  Reservation macro name

  <<Register name>>
  Register macro name
  Bit macro name
     :

  <<Register name>>
  Register macro name
  Bit macro name
     :

  (*) The channel/unit number, and register number in the macro name is shown
    by [...].
    [0-4] means 0,1,2,3,4
    [00/02/04] means 00,02,04

    Example)
      CAN[00-02] : CAN00, CAN01, CAN02
      BT_BTSEL[23/45/67/89/1011] : means BT_BTSEL23, BT_BTSEL45,
                                         BT_BTSEL67, BT_BTSEL89, BT_BTSEL1011

  (*) If there is "Note : Register macro name is not used.", the corresponding
    register macro is not provided.
    If only two or more register numbers exist and a part of the registers are
    a reservation area, the expression above is used. 

    Example)      
      PPC_PCFGR[000-031/100-131/200-231/300-331/400-431]
      Note : PPC_PCFGR[130/307-308/331/400-406/424] is not used.
           : PPC_PCFGR[130/307-308/331/400-406/424] does not offer the
             corresponding registers.


7.Notes
  Be careful when you use the following I/O registers. Because there is danger
  of causing the malfunction when you use the bit macros.

    [1] The access sizes of the registers are restricted.
    [2] In the register, there is a bit which is prohibited from writing the
        reading value.
        (Example : bit attribute is R0,W1)

  In case of [1], please do not use the bit macros, and use the register macros
  for both reading and writing.
  In case of [2], please use the register macro for writing, and use the bit
  macro for reading only.
  If the register that corresponds to either [1] or [2] and the register has
  the write only bit, the I/O register file does not provide the bit macro.

  Reason why bit macros cause malfunction
    Because the access sizes are compiler dependence, the accesses by the bit
    field member has danger of violating the restriction of the access size.
    Moreover, the usual writing might destroy the bits that hardware has set
    or write a value not allowed in the reservation bits because the
    usual writing is done with Read-Modify-Write.


8.History

  ----------------------------------------------------------------------------
  Version  Date        Content
  ----------------------------------------------------------------------------
  1.0      2017/03/15  First Edition

  ----------------------------------------------------------------------------
  

+-----------------------------------------------------------------------------+
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