<<Reserved symbol>>
TPU0

<<TPU0_UNLOCK>>
TPU0_UNLOCK
TPU0_UNLOCK_UNLOCK

<<TPU0_LST>>
TPU0_LST
TPU0_LST_LST

<<TPU0_CFG>>
TPU0_CFG
TPU0_CFG_INTE
TPU0_CFG_GLBPS
TPU0_CFG_GLBPSE
TPU0_CFG_DBGE

<<TPU0_TIR>>
TPU0_TIR
TPU0_TIR_IR0
TPU0_TIR_IR1
TPU0_TIR_IR2
TPU0_TIR_IR3
TPU0_TIR_IR4
TPU0_TIR_IR5
TPU0_TIR_IR6
TPU0_TIR_IR7

<<TPU0_TST>>
TPU0_TST
TPU0_TST_ST0
TPU0_TST_ST1
TPU0_TST_ST2
TPU0_TST_ST3
TPU0_TST_ST4
TPU0_TST_ST5
TPU0_TST_ST6
TPU0_TST_ST7

<<TPU0_TIE>>
TPU0_TIE
TPU0_TIE_IE0
TPU0_TIE_IE1
TPU0_TIE_IE2
TPU0_TIE_IE3
TPU0_TIE_IE4
TPU0_TIE_IE5
TPU0_TIE_IE6
TPU0_TIE_IE7

<<TPU0_TCN0x>>
TPU0_TCN0[0-7]
TPU0_TCN0[0-7]_ECPL
TPU0_TCN0[0-7]_IRC
TPU0_TCN0[0-7]_IEC
TPU0_TCN0[0-7]_IES
TPU0_TCN0[0-7]_CONT
TPU0_TCN0[0-7]_STOP
TPU0_TCN0[0-7]_START

<<TPU0_TCN1x>>
TPU0_TCN1[0-7]
TPU0_TCN1[0-7]_PS
TPU0_TCN1[0-7]_TMOD
TPU0_TCN1[0-7]_FRT
TPU0_TCN1[0-7]_PL

<<TPU0_TCCx>>
TPU0_TCC[0-7]
TPU0_TCC[0-7]_TCC

