<<Reserved symbol>>
I2S[0-1]

<<I2Sx_RXFDATx>>
I2S[0-1]_RXFDAT[0-15]
I2S[0-1]_RXFDAT[0-15]_RXDATA

<<I2Sx_TXFDATx>>
I2S[0-1]_TXFDAT[0-15]
I2S[0-1]_TXFDAT[0-15]_TXDATA

<<I2Sx_CNTREG>>
I2S[0-1]_CNTREG
I2S[0-1]_CNTREG_FSPL
I2S[0-1]_CNTREG_FSLN
I2S[0-1]_CNTREG_FSPH
I2S[0-1]_CNTREG_CPOL
I2S[0-1]_CNTREG_SMPL
I2S[0-1]_CNTREG_RXDIS
I2S[0-1]_CNTREG_TXDIS
I2S[0-1]_CNTREG_MSLB
I2S[0-1]_CNTREG_FRUN
I2S[0-1]_CNTREG_BEXT
I2S[0-1]_CNTREG_ECKM
I2S[0-1]_CNTREG_RHLL
I2S[0-1]_CNTREG_SBFN
I2S[0-1]_CNTREG_MSMD
I2S[0-1]_CNTREG_MSKB
I2S[0-1]_CNTREG_OVHD
I2S[0-1]_CNTREG_CKRT

<<I2Sx_MCR0REG>>
I2S[0-1]_MCR0REG
I2S[0-1]_MCR0REG_S0WDL
I2S[0-1]_MCR0REG_S0CHL
I2S[0-1]_MCR0REG_S0CHN
I2S[0-1]_MCR0REG_S1WDL
I2S[0-1]_MCR0REG_S1CHL
I2S[0-1]_MCR0REG_S1CHN

<<I2Sx_MCR1REG>>
I2S[0-1]_MCR1REG
I2S[0-1]_MCR1REG_S0CH0
I2S[0-1]_MCR1REG_S0CH1
I2S[0-1]_MCR1REG_S0CH2
I2S[0-1]_MCR1REG_S0CH3
I2S[0-1]_MCR1REG_S0CH4
I2S[0-1]_MCR1REG_S0CH5
I2S[0-1]_MCR1REG_S0CH6
I2S[0-1]_MCR1REG_S0CH7
I2S[0-1]_MCR1REG_S0CH8
I2S[0-1]_MCR1REG_S0CH9
I2S[0-1]_MCR1REG_S0CH10
I2S[0-1]_MCR1REG_S0CH11
I2S[0-1]_MCR1REG_S0CH12
I2S[0-1]_MCR1REG_S0CH13
I2S[0-1]_MCR1REG_S0CH14
I2S[0-1]_MCR1REG_S0CH15
I2S[0-1]_MCR1REG_S0CH16
I2S[0-1]_MCR1REG_S0CH17
I2S[0-1]_MCR1REG_S0CH18
I2S[0-1]_MCR1REG_S0CH19
I2S[0-1]_MCR1REG_S0CH20
I2S[0-1]_MCR1REG_S0CH21
I2S[0-1]_MCR1REG_S0CH22
I2S[0-1]_MCR1REG_S0CH23
I2S[0-1]_MCR1REG_S0CH24
I2S[0-1]_MCR1REG_S0CH25
I2S[0-1]_MCR1REG_S0CH26
I2S[0-1]_MCR1REG_S0CH27
I2S[0-1]_MCR1REG_S0CH28
I2S[0-1]_MCR1REG_S0CH29
I2S[0-1]_MCR1REG_S0CH30
I2S[0-1]_MCR1REG_S0CH31

<<I2Sx_MCR2REG>>
I2S[0-1]_MCR2REG
I2S[0-1]_MCR2REG_S1CH0
I2S[0-1]_MCR2REG_S1CH1
I2S[0-1]_MCR2REG_S1CH2
I2S[0-1]_MCR2REG_S1CH3
I2S[0-1]_MCR2REG_S1CH4
I2S[0-1]_MCR2REG_S1CH5
I2S[0-1]_MCR2REG_S1CH6
I2S[0-1]_MCR2REG_S1CH7
I2S[0-1]_MCR2REG_S1CH8
I2S[0-1]_MCR2REG_S1CH9
I2S[0-1]_MCR2REG_S1CH10
I2S[0-1]_MCR2REG_S1CH11
I2S[0-1]_MCR2REG_S1CH12
I2S[0-1]_MCR2REG_S1CH13
I2S[0-1]_MCR2REG_S1CH14
I2S[0-1]_MCR2REG_S1CH15
I2S[0-1]_MCR2REG_S1CH16
I2S[0-1]_MCR2REG_S1CH17
I2S[0-1]_MCR2REG_S1CH18
I2S[0-1]_MCR2REG_S1CH19
I2S[0-1]_MCR2REG_S1CH20
I2S[0-1]_MCR2REG_S1CH21
I2S[0-1]_MCR2REG_S1CH22
I2S[0-1]_MCR2REG_S1CH23
I2S[0-1]_MCR2REG_S1CH24
I2S[0-1]_MCR2REG_S1CH25
I2S[0-1]_MCR2REG_S1CH26
I2S[0-1]_MCR2REG_S1CH27
I2S[0-1]_MCR2REG_S1CH28
I2S[0-1]_MCR2REG_S1CH29
I2S[0-1]_MCR2REG_S1CH30
I2S[0-1]_MCR2REG_S1CH31

<<I2Sx_OPRREG>>
I2S[0-1]_OPRREG
I2S[0-1]_OPRREG_START
I2S[0-1]_OPRREG_TXENB
I2S[0-1]_OPRREG_RXENB

<<I2Sx_SRST>>
I2S[0-1]_SRST
I2S[0-1]_SRST_SRST

<<I2Sx_INTCNT>>
I2S[0-1]_INTCNT
I2S[0-1]_INTCNT_RFTH
I2S[0-1]_INTCNT_RPTMR
I2S[0-1]_INTCNT_TFTH
I2S[0-1]_INTCNT_RXFIM
I2S[0-1]_INTCNT_RXFDM
I2S[0-1]_INTCNT_EOPM
I2S[0-1]_INTCNT_RXOVM
I2S[0-1]_INTCNT_RXUDM
I2S[0-1]_INTCNT_RBERM
I2S[0-1]_INTCNT_TXFIM
I2S[0-1]_INTCNT_TXFDM
I2S[0-1]_INTCNT_TXOVM
I2S[0-1]_INTCNT_TXUD0M
I2S[0-1]_INTCNT_FERRM
I2S[0-1]_INTCNT_TBERM
I2S[0-1]_INTCNT_TXUD1M

<<I2Sx_STATUS>>
I2S[0-1]_STATUS
I2S[0-1]_STATUS_RXNUM
I2S[0-1]_STATUS_TXNUM
I2S[0-1]_STATUS_RXFI
I2S[0-1]_STATUS_TXFI
I2S[0-1]_STATUS_BSY
I2S[0-1]_STATUS_EOPI
I2S[0-1]_STATUS_RXOVR
I2S[0-1]_STATUS_RXUDR
I2S[0-1]_STATUS_TXOVR
I2S[0-1]_STATUS_TXUDR0
I2S[0-1]_STATUS_TXUDR1
I2S[0-1]_STATUS_FERR
I2S[0-1]_STATUS_RBERR
I2S[0-1]_STATUS_TBERR

<<I2Sx_DMAACT>>
I2S[0-1]_DMAACT
I2S[0-1]_DMAACT_RDMACT
I2S[0-1]_DMAACT_TDMACT

<<I2Sx_DEBUG>>
I2S[0-1]_DEBUG
I2S[0-1]_DEBUG_DBGE

<<I2Sx_MIDREG>>
I2S[0-1]_MIDREG
I2S[0-1]_MIDREG_MID

