/****************************************************************************
 *  License : All rights reserved for TES Electronic Solutions GmbH
 *            See included /docs/license.txt for details
 *  Project : D/AVE HD
 *  Purpose : HW Register defaults
 ****************************************************************************
 * Version Control Information :
 * DO NOT EDIT THIS FILE - This file will be automatically generated by
 * 'gen_register_headers_sw.py'
 ****************************************************************************
 * Change History (autogenerated):
 ****************************************************************************/    

/*----------------------------------------------------------------------------------------------------------*/
/* All register defaults                                                                                    */
/*                                                                                                          */

#if defined (__ghs__)
#pragma ghs startnomisra
#endif /* __ghs__ */

#include "davehd_registertypes.h"
#ifndef E_BOOL_TRUE
  #define E_BOOL_TRUE DHD_TRUE
#endif
#ifndef E_BOOL_FALSE
  #define E_BOOL_FALSE DHD_FALSE
#endif
const dhd_uint32_t dhd_reset_state[] = {
(0x0 << 16) | (0x0 << 0), /* PSU_Lim_Bbox_Min*/
(0x0 << 16) | (0x0 << 0), /* PSU_Lim_Bbox_Max*/
(0x0 << 16), /* PSU_Lim_Start*/
(0x0 << 28) | (0x0 << 20) | (0x0 << 16) | (0x0 << 12) | (0x0 << 8) | (0x0 << 4) | (0x0 << 0), /* PSU_Lim_Ctrl*/
(0x0 << 16) | (0x0 << 0), /* PSU_Lim_Stripe*/
(0x0 << 0), /* PSU_Bez_Ctrl*/
(0x0 << 0), /* PSU_Bez_Voff_0*/
(0x0 << 0), /* PSU_Bez_Voff_1*/
(0x0 << 16) | (0x0 << 8) | (0x0 << 0), /* PSU_Bez_AA_Ctrl*/
(0x0 << 0), /* PSU_Lim_Vstart_0*/
(0x0 << 0), /* PSU_Lim_dx_0*/
(0x0 << 0), /* PSU_Lim_dy_0*/
(0x0 << 0), /* PSU_Lim_Vstart_1*/
(0x0 << 0), /* PSU_Lim_dx_1*/
(0x0 << 0), /* PSU_Lim_dy_1*/
(0x0 << 0), /* PSU_Lim_Vstart_2*/
(0x0 << 0), /* PSU_Lim_dx_2*/
(0x0 << 0), /* PSU_Lim_dy_2*/
(0x0 << 0), /* PSU_Lim_Vstart_3*/
(0x0 << 0), /* PSU_Lim_dx_3*/
(0x0 << 0), /* PSU_Lim_dy_3*/
(0x0 << 0), /* PSU_Lim_Vstart_4*/
(0x0 << 0), /* PSU_Lim_dx_4*/
(0x0 << 0), /* PSU_Lim_dy_4*/
(0x0 << 0), /* PSU_Lim_Vstart_5*/
(0x0 << 0), /* PSU_Lim_dx_5*/
(0x0 << 0), /* PSU_Lim_dy_5*/
(0x0 << 4) | (0x0 << 0), /* PSU_Debug_Ctrl*/
(0xfff << 16) | (0xfff << 0), /* PSU_Lim_Max_Coord*/
(0x0 << 0), /* TXA_U_Offset_0*/
(0x0 << 0), /* TXA_V_Offset_0*/
(0x3f800000 << 0), /* TXA_dUX_0*/
(0x0 << 0), /* TXA_dUY_0*/
(0x0 << 0), /* TXA_dVX_0*/
(0x3f800000 << 0), /* TXA_dVY_0*/
(0x0 << 0), /* TXA_U_Offset_1*/
(0x0 << 0), /* TXA_V_Offset_1*/
(0x3f800000 << 0), /* TXA_dUX_1*/
(0x0 << 0), /* TXA_dUY_1*/
(0x0 << 0), /* TXA_dVX_1*/
(0x3f800000 << 0), /* TXA_dVY_1*/
(0x0 << 0), /* ZSS_Pitch*/
(0xff << 0), /* ZSS_Span_Config*/
(0x0 << 0), /* TXA_Z_Offset*/
(0x0 << 0), /* TXA_dZX*/
(0x0 << 0), /* TXA_dZY*/
(0x3f800000 << 0), /* TXA_Z_RHW_Offset*/
(0x0 << 0), /* TXA_Z_dRHWX*/
(0x0 << 0), /* TXA_Z_dRHWY*/
(0x3f800000 << 0), /* TXA_RHW_Offset_0*/
(0x0 << 0), /* TXA_dRHWX_0*/
(0x0 << 0), /* TXA_dRHWY_0*/
(0x3f800000 << 0), /* TXA_RHW_Offset_1*/
(0x0 << 0), /* TXA_dRHWX_1*/
(0x0 << 0), /* TXA_dRHWY_1*/
(E_BOOL_TRUE << 8) | (E_BOOL_FALSE << 4) | (E_ZSA_ORG_S8A8Z16 << 0), /* ZSA_Ctrl*/
(0x0 << 0), /* ZSC_Start_Address*/
(E_STENCIL_OP_KEEP << 24) | (E_STENCIL_OP_KEEP << 20) | (E_STENCIL_OP_KEEP << 16) | (E_STENCIL_FUNC_ALWAYS << 12) | (E_BOOL_FALSE << 9) | (E_BOOL_FALSE << 8) | (E_DEPTH_FUNC_ALWAYS << 4) | (E_ALPHA_MASK_WRITE_MODE_KEEP << 2) | (E_ALPHA_MASK_MODE_MULTIPLY << 1) | (E_BOOL_FALSE << 0), /* ZSU_Ctrl1*/
(0x0 << 24) | (0xff << 16) | (0x0 << 8) | (0xff << 0), /* ZSU_Ctrl2*/
(0x0 << 16) | (0x0 << 0), /* TXA_Size_0*/
(E_FILTER_SAMPLE_SHAPE_QUAD << 30) | (0x1 << 24) | (0x1 << 16) | (0x0 << 0), /* TXA_Access_0*/
(0x0 << 16) | (0x0 << 0), /* TXA_Size_1*/
(E_FILTER_SAMPLE_SHAPE_QUAD << 30) | (0x1 << 24) | (0x1 << 16) | (0x0 << 0), /* TXA_Access_1*/
(E_TXC_DEBUG_MODE_NONE << 30) | (0x0 << 12) | (E_BOOL_FALSE << 4) | (0x0 << 0), /* TEX_Global*/
(0x1 << 0), /* COL_Global*/
(0x0 << 8) | (0x0 << 4) | (E_ALPHA_TEST_OP_ALWAYS << 0), /* FBD_Config*/
(E_BOOL_FALSE << 16) | (0x0 << 0), /* FBS_Pitch*/
(0x10 << 16) | (0xff << 0), /* FBS_Span_Config*/
(0x0 << 0), /* RLD_Start_Address*/
(0xffffffff << 0), /* COL_Const_Color_0*/
(0xffffffff << 0), /* COL_Const_Color_1*/
(0xffffffff << 0), /* COL_Const_Color_2*/
(0xffffffff << 0), /* COL_Const_Color_3*/
(E_BOOL_FALSE << 28) | (0x0 << 24) | (E_TEX_VIRTUAL_TILING_MODE_OFF << 20) | (E_SWIZZLE_MODE_LINEAR << 16) | (E_BOOL_FALSE << 13) | (E_TEXEL_ORG_ARGB_8888 << 8) | (E_BOOL_FALSE << 7) | (E_WRAP_MODE_CLAMP << 4) | (E_BOOL_FALSE << 3) | (E_WRAP_MODE_CLAMP << 0), /* TEX_Mode_0*/
(0x0 << 0), /* TXC_Start_Address_0*/
(0x0 << 16) | (E_BOOL_FALSE << 8) | (E_BOOL_FALSE << 4) | (E_TEX_CLUT_MODE_OFF << 0), /* TXP_Ctrl_0*/
(0x0 << 0), /* TXP_Clut_Offset_0*/
(0x0 << 0), /* TXP_Color_Key_0*/
(0x0 << 0), /* TXP_Fill_Color_0*/
(0x0 << 20) | (0x0 << 12) | (0x1 << 0), /* TXP_Filter_Scale_Bias_0*/
(E_BOOL_FALSE << 28) | (0x0 << 24) | (E_TEX_VIRTUAL_TILING_MODE_OFF << 20) | (E_SWIZZLE_MODE_LINEAR << 16) | (E_BOOL_FALSE << 13) | (E_TEXEL_ORG_ARGB_8888 << 8) | (E_BOOL_FALSE << 7) | (E_WRAP_MODE_CLAMP << 4) | (E_BOOL_FALSE << 3) | (E_WRAP_MODE_CLAMP << 0), /* TEX_Mode_1*/
(0x0 << 0), /* TXC_Start_Address_1*/
(0x0 << 16) | (E_BOOL_FALSE << 8) | (E_BOOL_FALSE << 4) | (E_TEX_CLUT_MODE_OFF << 0), /* TXP_Ctrl_1*/
(0x0 << 0), /* TXP_Clut_Offset_1*/
(0x0 << 0), /* TXP_Color_Key_1*/
(0x0 << 0), /* TXP_Fill_Color_1*/
(0x0 << 20) | (0x0 << 12) | (0x1 << 0), /* TXP_Filter_Scale_Bias_1*/
(E_BOOL_FALSE << 30) | (E_COL_OP_INVERT_MODE_NO_INVERSION << 28) | (E_COL_OP_SELECT_ARGB_USE_A << 24) | (E_COL_OP_SELECT_INPUT_CONST_0 << 16) | (E_BOOL_FALSE << 14) | (E_COL_OP_INVERT_MODE_NO_INVERSION << 12) | (E_COL_OP_SELECT_ARGB_USE_R << 10) | (E_COL_OP_SELECT_ARGB_USE_G << 8) | (E_COL_OP_SELECT_ARGB_USE_B << 6) | (E_COL_OP_SELECT_INPUT_CONST_0 << 0), /* COL_ARGB_Op1a_0*/
(E_BOOL_FALSE << 31) | (E_BOOL_FALSE << 30) | (E_COL_OP_INVERT_MODE_NO_INVERSION << 28) | (E_COL_OP_SELECT_ARGB_USE_A << 24) | (E_COL_OP_SELECT_INPUT_CONST_0 << 16) | (E_BOOL_FALSE << 15) | (E_BOOL_FALSE << 14) | (E_COL_OP_INVERT_MODE_NO_INVERSION << 12) | (E_COL_OP_SELECT_ARGB_USE_R << 10) | (E_COL_OP_SELECT_ARGB_USE_G << 8) | (E_COL_OP_SELECT_ARGB_USE_B << 6) | (E_COL_OP_SELECT_INPUT_CONST_0 << 0), /* COL_ARGB_Op1b_0*/
(E_BOOL_FALSE << 30) | (E_COL_OP_INVERT_MODE_NO_INVERSION << 28) | (E_COL_OP_SELECT_ARGB_USE_A << 24) | (E_COL_OP_SELECT_INPUT_CONST_0 << 16) | (E_BOOL_FALSE << 14) | (E_COL_OP_INVERT_MODE_NO_INVERSION << 12) | (E_COL_OP_SELECT_ARGB_USE_R << 10) | (E_COL_OP_SELECT_ARGB_USE_G << 8) | (E_COL_OP_SELECT_ARGB_USE_B << 6) | (E_COL_OP_SELECT_INPUT_CONST_0 << 0), /* COL_ARGB_Op2a_0*/
(E_BOOL_FALSE << 31) | (E_BOOL_FALSE << 30) | (E_COL_OP_INVERT_MODE_NO_INVERSION << 28) | (E_COL_OP_SELECT_ARGB_USE_A << 24) | (E_COL_OP_SELECT_INPUT_CONST_0 << 16) | (E_BOOL_FALSE << 15) | (E_BOOL_FALSE << 14) | (E_COL_OP_INVERT_MODE_NO_INVERSION << 12) | (E_COL_OP_SELECT_ARGB_USE_R << 10) | (E_COL_OP_SELECT_ARGB_USE_G << 8) | (E_COL_OP_SELECT_ARGB_USE_B << 6) | (E_COL_OP_SELECT_INPUT_CONST_0 << 0), /* COL_ARGB_Op2b_0*/
(E_BOOL_FALSE << 30) | (E_COL_OP_INVERT_MODE_NO_INVERSION << 28) | (E_COL_OP_SELECT_ARGB_USE_A << 24) | (E_COL_OP_SELECT_INPUT_COLOR_0 << 16) | (E_BOOL_FALSE << 14) | (E_COL_OP_INVERT_MODE_NO_INVERSION << 12) | (E_COL_OP_SELECT_ARGB_USE_R << 10) | (E_COL_OP_SELECT_ARGB_USE_G << 8) | (E_COL_OP_SELECT_ARGB_USE_B << 6) | (E_COL_OP_SELECT_INPUT_COLOR_0 << 0), /* COL_ARGB_Op3_0*/
(E_BOOL_TRUE << 28) | (E_COL_SCALE_OUT_NO_SHIFT << 16) | (E_BOOL_TRUE << 12) | (E_COL_SCALE_OUT_NO_SHIFT << 0), /* COL_ARGB_Out_0*/
(E_BOOL_FALSE << 30) | (E_COL_OP_INVERT_MODE_NO_INVERSION << 28) | (E_COL_OP_SELECT_ARGB_USE_A << 24) | (E_COL_OP_SELECT_INPUT_CONST_0 << 16) | (E_BOOL_FALSE << 14) | (E_COL_OP_INVERT_MODE_NO_INVERSION << 12) | (E_COL_OP_SELECT_ARGB_USE_R << 10) | (E_COL_OP_SELECT_ARGB_USE_G << 8) | (E_COL_OP_SELECT_ARGB_USE_B << 6) | (E_COL_OP_SELECT_INPUT_CONST_0 << 0), /* COL_ARGB_Op1a_1*/
(E_BOOL_FALSE << 31) | (E_BOOL_FALSE << 30) | (E_COL_OP_INVERT_MODE_NO_INVERSION << 28) | (E_COL_OP_SELECT_ARGB_USE_A << 24) | (E_COL_OP_SELECT_INPUT_CONST_0 << 16) | (E_BOOL_FALSE << 15) | (E_BOOL_FALSE << 14) | (E_COL_OP_INVERT_MODE_NO_INVERSION << 12) | (E_COL_OP_SELECT_ARGB_USE_R << 10) | (E_COL_OP_SELECT_ARGB_USE_G << 8) | (E_COL_OP_SELECT_ARGB_USE_B << 6) | (E_COL_OP_SELECT_INPUT_CONST_0 << 0), /* COL_ARGB_Op1b_1*/
(E_BOOL_FALSE << 30) | (E_COL_OP_INVERT_MODE_NO_INVERSION << 28) | (E_COL_OP_SELECT_ARGB_USE_A << 24) | (E_COL_OP_SELECT_INPUT_CONST_0 << 16) | (E_BOOL_FALSE << 14) | (E_COL_OP_INVERT_MODE_NO_INVERSION << 12) | (E_COL_OP_SELECT_ARGB_USE_R << 10) | (E_COL_OP_SELECT_ARGB_USE_G << 8) | (E_COL_OP_SELECT_ARGB_USE_B << 6) | (E_COL_OP_SELECT_INPUT_CONST_0 << 0), /* COL_ARGB_Op2a_1*/
(E_BOOL_FALSE << 31) | (E_BOOL_FALSE << 30) | (E_COL_OP_INVERT_MODE_NO_INVERSION << 28) | (E_COL_OP_SELECT_ARGB_USE_A << 24) | (E_COL_OP_SELECT_INPUT_CONST_0 << 16) | (E_BOOL_FALSE << 15) | (E_BOOL_FALSE << 14) | (E_COL_OP_INVERT_MODE_NO_INVERSION << 12) | (E_COL_OP_SELECT_ARGB_USE_R << 10) | (E_COL_OP_SELECT_ARGB_USE_G << 8) | (E_COL_OP_SELECT_ARGB_USE_B << 6) | (E_COL_OP_SELECT_INPUT_CONST_0 << 0), /* COL_ARGB_Op2b_1*/
(E_BOOL_FALSE << 30) | (E_COL_OP_INVERT_MODE_NO_INVERSION << 28) | (E_COL_OP_SELECT_ARGB_USE_A << 24) | (E_COL_OP_SELECT_INPUT_COLOR_0 << 16) | (E_BOOL_FALSE << 14) | (E_COL_OP_INVERT_MODE_NO_INVERSION << 12) | (E_COL_OP_SELECT_ARGB_USE_R << 10) | (E_COL_OP_SELECT_ARGB_USE_G << 8) | (E_COL_OP_SELECT_ARGB_USE_B << 6) | (E_COL_OP_SELECT_INPUT_COLOR_0 << 0), /* COL_ARGB_Op3_1*/
(E_BOOL_TRUE << 28) | (E_COL_SCALE_OUT_NO_SHIFT << 16) | (E_BOOL_TRUE << 12) | (E_COL_SCALE_OUT_NO_SHIFT << 0), /* COL_ARGB_Out_1*/
(E_BOOL_FALSE << 30) | (E_COL_OP_INVERT_MODE_NO_INVERSION << 28) | (E_COL_OP_SELECT_ARGB_USE_A << 24) | (E_COL_OP_SELECT_INPUT_CONST_0 << 16) | (E_BOOL_FALSE << 14) | (E_COL_OP_INVERT_MODE_NO_INVERSION << 12) | (E_COL_OP_SELECT_ARGB_USE_R << 10) | (E_COL_OP_SELECT_ARGB_USE_G << 8) | (E_COL_OP_SELECT_ARGB_USE_B << 6) | (E_COL_OP_SELECT_INPUT_CONST_0 << 0), /* COL_ARGB_Op1a_2*/
(E_BOOL_FALSE << 31) | (E_BOOL_FALSE << 30) | (E_COL_OP_INVERT_MODE_NO_INVERSION << 28) | (E_COL_OP_SELECT_ARGB_USE_A << 24) | (E_COL_OP_SELECT_INPUT_CONST_0 << 16) | (E_BOOL_FALSE << 15) | (E_BOOL_FALSE << 14) | (E_COL_OP_INVERT_MODE_NO_INVERSION << 12) | (E_COL_OP_SELECT_ARGB_USE_R << 10) | (E_COL_OP_SELECT_ARGB_USE_G << 8) | (E_COL_OP_SELECT_ARGB_USE_B << 6) | (E_COL_OP_SELECT_INPUT_CONST_0 << 0), /* COL_ARGB_Op1b_2*/
(E_BOOL_FALSE << 30) | (E_COL_OP_INVERT_MODE_NO_INVERSION << 28) | (E_COL_OP_SELECT_ARGB_USE_A << 24) | (E_COL_OP_SELECT_INPUT_CONST_0 << 16) | (E_BOOL_FALSE << 14) | (E_COL_OP_INVERT_MODE_NO_INVERSION << 12) | (E_COL_OP_SELECT_ARGB_USE_R << 10) | (E_COL_OP_SELECT_ARGB_USE_G << 8) | (E_COL_OP_SELECT_ARGB_USE_B << 6) | (E_COL_OP_SELECT_INPUT_CONST_0 << 0), /* COL_ARGB_Op2a_2*/
(E_BOOL_FALSE << 31) | (E_BOOL_FALSE << 30) | (E_COL_OP_INVERT_MODE_NO_INVERSION << 28) | (E_COL_OP_SELECT_ARGB_USE_A << 24) | (E_COL_OP_SELECT_INPUT_CONST_0 << 16) | (E_BOOL_FALSE << 15) | (E_BOOL_FALSE << 14) | (E_COL_OP_INVERT_MODE_NO_INVERSION << 12) | (E_COL_OP_SELECT_ARGB_USE_R << 10) | (E_COL_OP_SELECT_ARGB_USE_G << 8) | (E_COL_OP_SELECT_ARGB_USE_B << 6) | (E_COL_OP_SELECT_INPUT_CONST_0 << 0), /* COL_ARGB_Op2b_2*/
(E_BOOL_FALSE << 30) | (E_COL_OP_INVERT_MODE_NO_INVERSION << 28) | (E_COL_OP_SELECT_ARGB_USE_A << 24) | (E_COL_OP_SELECT_INPUT_COLOR_0 << 16) | (E_BOOL_FALSE << 14) | (E_COL_OP_INVERT_MODE_NO_INVERSION << 12) | (E_COL_OP_SELECT_ARGB_USE_R << 10) | (E_COL_OP_SELECT_ARGB_USE_G << 8) | (E_COL_OP_SELECT_ARGB_USE_B << 6) | (E_COL_OP_SELECT_INPUT_COLOR_0 << 0), /* COL_ARGB_Op3_2*/
(E_BOOL_TRUE << 28) | (E_COL_SCALE_OUT_NO_SHIFT << 16) | (E_BOOL_TRUE << 12) | (E_COL_SCALE_OUT_NO_SHIFT << 0), /* COL_ARGB_Out_2*/
(E_BOOL_FALSE << 5) | (E_PIXEL_ORG_ARGB_8888 << 0), /* FB_Pixel_Org*/
(0x0 << 0), /* FBC_Start_Address*/
(E_BOOL_FALSE << 31) | (E_BOOL_FALSE << 30) | (E_ALPHA_BLEND_MODE_BLEND << 28) | (E_BOOL_FALSE << 25) | (E_BOOL_TRUE << 24) | (E_BLEND_FACTOR_SELECT_ZERO << 20) | (E_BLEND_FACTOR_SELECT_ZERO << 16) | (E_COLOR_BLEND_MODE_BLEND << 12) | (E_BOOL_TRUE << 11) | (E_BOOL_TRUE << 10) | (E_BOOL_FALSE << 9) | (E_BOOL_TRUE << 8) | (E_BLEND_FACTOR_SELECT_ZERO << 4) | (E_BLEND_FACTOR_SELECT_ZERO << 0), /* BLU_Blend*/
(0x0 << 24) | (0x0 << 20) | (0x0 << 16) | (0x0 << 4) | (E_BOOL_FALSE << 0), /* BLU_Dither*/
(E_BOOL_FALSE << 17) | (E_BOOL_TRUE << 16) | (E_BOOL_TRUE << 3) | (E_BOOL_TRUE << 2) | (E_BOOL_TRUE << 1) | (E_BOOL_TRUE << 0), /* BLU_Write*/
(E_BOOL_FALSE << 3) | (E_BOOL_FALSE << 2) | (E_BOOL_FALSE << 1) | (E_BOOL_FALSE << 0), /* PFC_Enable*/
(E_BOOL_FALSE << 3) | (E_BOOL_FALSE << 2) | (E_BOOL_FALSE << 1) | (E_BOOL_FALSE << 0), /* PFC_Clear*/
(E_PFC_EVENT_STC_BUSY << 0), /* PFC_Event_Select_0*/
(E_PFC_EVENT_STC_BUSY << 0), /* PFC_Event_Select_1*/
(E_PFC_EVENT_STC_BUSY << 0), /* PFC_Event_Select_2*/
(E_PFC_EVENT_STC_BUSY << 0), /* PFC_Event_Select_3*/
(0xffffffff << 0), /* CLR_Value*/
(0x0 << 16) | (0x0 << 0), /* CLR_Line_Config*/
(0xf << 16) | (0x0 << 0), /* CLR_Ctrl*/
(0x0 << 0), /* CLR_Start_Address*/
};

#if defined (__ghs__)
#pragma ghs endnomisra
#endif /* __ghs__ */
