1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
/*
****************************************************************************
PROJECT : TAUJ driver
FILE : $Id: r_tauj_regs.h 7640 2016-02-12 13:14:23Z florian.zimmermann $
============================================================================
DESCRIPTION
Driver for TAUJ macro
============================================================================
C O P Y R I G H T
============================================================================
Copyright (c) 2013 - 2014
by
Renesas Electronics (Europe) GmbH.
Arcadiastrasse 10
D-40472 Duesseldorf
Germany
All rights reserved.
============================================================================
Purpose: only for testing, not for mass production
DISCLAIMER
LICENSEE has read, understood and accepted the terms and conditions defined in
the license agreement, especially the usage rights. In any case, it is
LICENSEE's responsibility to make sure that any user of the software complies
with the terms and conditions of the signed license agreement.
SAMPLE CODE is not part of the licensed software, as such it must not be used in
mass-production applications. It can only be used for evaluation and
demonstration purposes at customer's premises listed in the signed license
agreement.
****************************************************************************
*/
#ifndef R_TAUJ_REGS_H_
#define R_TAUJ_REGS_H_
#ifdef __cplusplus
extern "C" {
#endif
/***********************************************************
Title: TAUJ Register Offsets
Only the driver modules shall include this header.
*/
/***********************************************************
Section: Global Defines
*/
#ifndef R_TAUJ_USER_OFFSET
#define R_TAUJ_USER_OFFSET( x ) ( 0x00000000 )
#endif
#ifndef R_TAUJ_OS_OFFSET
#define R_TAUJ_OS_OFFSET( x ) ( 0x00000000 )
#endif
/***********************************************************
Constants: Register Offsets
*/
/* Channel Data Register 0 R/W (16 and 32 bit) */
#define R_TAUJ0_CDR0 ( R_TAUJ_USER_OFFSET( Unit ) + 0x0000 )
/* Channel Data Register 1 R/W (16 and 32 bit) */
#define R_TAUJ0_CDR1 ( R_TAUJ_USER_OFFSET( Unit ) + 0x0004 )
/* Channel Data Register 2 R/W (16 and 32 bit) */
#define R_TAUJ0_CDR2 ( R_TAUJ_USER_OFFSET( Unit ) + 0x0008 )
/* Channel Data Register 3 R/W (16 and 32 bit) */
#define R_TAUJ0_CDR3 ( R_TAUJ_USER_OFFSET( Unit ) + 0x000C )
/* Channel Counter Register 0 R (16 and 32 bit) */
#define R_TAUJ0_CNT0 ( R_TAUJ_USER_OFFSET( Unit ) + 0x0010 )
/* Channel Counter Register 1 R (16 and 32 bit) */
#define R_TAUJ0_CNT1 ( R_TAUJ_USER_OFFSET( Unit ) + 0x0014 )
/* Channel Counter Register 2 R (16 and 32 bit) */
#define R_TAUJ0_CNT2 ( R_TAUJ_USER_OFFSET( Unit ) + 0x0018 )
/* Channel Counter Register 3 R (16 and 32 bit) */
#define R_TAUJ0_CNT3 ( R_TAUJ_USER_OFFSET( Unit ) + 0x001C )
/* Channel Mode OS Register 0 R/W */
#define R_TAUJ0_CMOR0 ( R_TAUJ_OS_OFFSET( Unit ) + 0x0080 )
/* Channel Mode OS Register 1 R/W */
#define R_TAUJ0_CMOR1 ( R_TAUJ_OS_OFFSET( Unit ) + 0x0084 )
/* Channel Mode OS Register 2 R/W */
#define R_TAUJ0_CMOR2 ( R_TAUJ_OS_OFFSET( Unit ) + 0x0088 )
/* Channel Mode OS Register 3 R/W */
#define R_TAUJ0_CMOR3 ( R_TAUJ_OS_OFFSET( Unit ) + 0x008C )
/* Channel Mode User Register 0 R/W */
#define R_TAUJ0_CMUR0 ( R_TAUJ_USER_OFFSET( Unit ) + 0x0020 )
/* Channel Mode User Register 1 R/W */
#define R_TAUJ0_CMUR1 ( R_TAUJ_USER_OFFSET( Unit ) + 0x0024 )
/* Channel Mode User Register 2 R/W */
#define R_TAUJ0_CMUR2 ( R_TAUJ_USER_OFFSET( Unit ) + 0x0028 )
/* Channel Mode User Register 3 R/W */
#define R_TAUJ0_CMUR3 ( R_TAUJ_USER_OFFSET( Unit ) + 0x002C )
/* Channel Status Register 0 R */
#define R_TAUJ0_CSR0 ( R_TAUJ_USER_OFFSET( Unit ) + 0x0030 )
/* Channel Status Register 1 R */
#define R_TAUJ0_CSR1 ( R_TAUJ_USER_OFFSET( Unit ) + 0x0034 )
/* Channel Status Register 2 R */
#define R_TAUJ0_CSR2 ( R_TAUJ_USER_OFFSET( Unit ) + 0x0038 )
/* Channel Status Register 3 R */
#define R_TAUJ0_CSR3 ( R_TAUJ_USER_OFFSET( Unit ) + 0x003C )
/* Channel Status Clear Trigger Register 0 W */
#define R_TAUJ0_CSC0 ( R_TAUJ_USER_OFFSET( Unit ) + 0x0040 )
/* Channel Status Clear Trigger Register 1 W */
#define R_TAUJ0_CSC1 ( R_TAUJ_USER_OFFSET( Unit ) + 0x0044 )
/* Channel Status Clear Trigger Register 2 W */
#define R_TAUJ0_CSC2 ( R_TAUJ_USER_OFFSET( Unit ) + 0x0048 )
/* Channel Status Clear Trigger Register 3 W */
#define R_TAUJ0_CSC3 ( R_TAUJ_USER_OFFSET( Unit ) + 0x004C )
/* Channel Enable Status Register R */
#define R_TAUJ0_TE ( R_TAUJ_USER_OFFSET( Unit ) + 0x0050 )
/* Channel Start Trigger Register W */
#define R_TAUJ0_TS ( R_TAUJ_USER_OFFSET( Unit ) + 0x0054 )
/* Channel Stop Trigger Register W */
#define R_TAUJ0_TT ( R_TAUJ_USER_OFFSET( Unit ) + 0x0058 )
/* Presaler Clock Select Register R/W */
#define R_TAUJ0_TPS ( R_TAUJ_OS_OFFSET( Unit ) + 0x0090 )
/* Presaler Baud Rate Setting Register R/W */
#define R_TAUJ0_BRS ( R_TAUJ_OS_OFFSET( Unit ) + 0x0094 )
/* Channel Output Register R/W */
#define R_TAUJ0_TO ( R_TAUJ_USER_OFFSET( Unit ) + 0x005C )
/* Channel Output Enable Register R/W */
#define R_TAUJ0_TOE ( R_TAUJ_USER_OFFSET( Unit ) + 0x0060 )
/* Channel Output Mode Register R/W */
#define R_TAUJ0_TOM ( R_TAUJ_OS_OFFSET( Unit ) + 0x0098 )
/* Channel Output Configuration Register R/W */
#define R_TAUJ0_TOC ( R_TAUJ_OS_OFFSET( Unit ) + 0x009C )
/* Channel Output Active Level Register R/W */
#define R_TAUJ0_TOL ( R_TAUJ_USER_OFFSET( Unit ) + 0x0064 )
/* Channel Reload Data Enable Register R/W */
#define R_TAUJ0_RDE ( R_TAUJ_OS_OFFSET( Unit ) + 0x00A0 )
/* Channel Reload Data Mode Register R/W */
#define R_TAUJ0_RDM ( R_TAUJ_OS_OFFSET( Unit ) + 0x00A4 )
/* Channel Reload Data Trigger Register W */
#define R_TAUJ0_RDT ( R_TAUJ_USER_OFFSET( Unit ) + 0x0068 )
/* Channel Reload Status Register R */
#define R_TAUJ0_RSF ( R_TAUJ_USER_OFFSET( Unit ) + 0x006C )
/* TAU Emulation Register R/W */
#define R_TAUJ0_EMU ( R_TAUJ_OS_OFFSET( Unit ) + 0x00A8 )
/***********************************************************
Type: r_tauj_RegCmorBits_t
Content of the TAUJ0CMORn: TAU Channel Mode OS Register
Members:
Cks - CKS1 and CKS0: Clock Select Bits
Ccs - CCS1 and CCS0: Count Clock Select Bits
Mas - MAS: Master Mode Bit
Sts - STS2 to STS0: Start Trigger Select Bits
Cos - COS1 and COS0: Capture Overflow Select Bits
Res - Reserved
Md - MD4 to MD0: Mode Control Bits
*/
typedef struct {
uint16_t Md0 : 1;
uint16_t Md : 4;
uint16_t Res : 1;
uint16_t Cos : 2;
uint16_t Sts : 3;
uint16_t Mas : 1;
uint16_t Ccs : 2;
uint16_t Cks : 2;
} r_tauj_RegCmorBits_t;
typedef union {
r_tauj_RegCmorBits_t Bits;
uint16_t Word;
} r_tauj_RegCmor_t;
/***********************************************************
Type: r_tauj_RegCmurBits_t
Content of the TAUJ0CMURn: TAU Channel Mode User Register
Members:
Res - Reserved
Tis - TIS1 and TIS0: TINn Edge Select Bits
*/
typedef struct {
uint16_t Tis : 2;
uint16_t Res : 14;
} r_tauj_RegCmurBits_t;
typedef union {
r_tauj_RegCmurBits_t Bits;
uint16_t Word;
} r_tauj_RegCmur_t;
/***********************************************************
Type: r_tauj_RegCsrBits_t
Content of the TAUJ0CSRn: TAU Channel Status Register
Members:
Res - Reserved
Rfu_Csf - Count Status Flag Bit (reserved)
Ovf - Overflow Flag Bit
*/
typedef struct {
uint16_t Ovf : 1;
uint16_t Rfu_Csf : 1;
uint16_t Res : 15;
} r_tauj_RegCsrBits_t;
typedef union {
r_tauj_RegCsrBits_t Bits;
uint16_t Word;
} r_tauj_RegCsr_t;
/***********************************************************
Type: r_tauj_RegCscBits_t
Content of the TAUJ0CSCn: TAU Channel Status Clear Register
Members:
Res - Reserved
Clov - Clear Overflow Flag Bit
*/
typedef struct {
uint16_t Clov : 1;
uint16_t Res : 15;
} r_tauj_RegCscBits_t;
typedef union {
r_tauj_RegCscBits_t Bits;
uint16_t Word;
} r_tauj_RegCsc_t;
/***********************************************************
Type: r_tauj_RegTpsBits_t
Content of the TAUJ0TPS: TAU Prescaler Clock Select Register
Members:
Pcs_Ck0 - Prescaler Clock Select Bits for CK0
Pcs_Ck1 - Prescaler Clock Select Bits for CK1
Pcs_Ck2 - Prescaler Clock Select Bits for CK2
Pcs_Ck3 - Prescaler Clock Select Bits for CK3
*/
typedef struct {
uint16_t Pcs_Ck0 : 4;
uint16_t Pcs_Ck1 : 4;
uint16_t Pcs_Ck2 : 4;
uint16_t Pcs_Ck3 : 4;
} r_tauj_RegTpsBits_t;
typedef union {
r_tauj_RegTpsBits_t Bits;
uint16_t Word;
} r_tauj_RegTps_t;
/***********************************************************
Type: r_tauj_RegBrsBits_t
Content of the TAUJ0BRS: TAU Prescaler Baud Rate Setting Register
Members:
Res - Reserved for future use
Brs - Baud rate clock setting for CK3 (8bit)
*/
typedef struct {
uint8_t Res : 8;
uint16_t Rfu : 8;
} r_tauj_RegBrsBits_t;
typedef union {
r_tauj_RegBrsBits_t Bits;
uint16_t Word;
} r_tauj_RegBrs_t;
/***********************************************************
Type: r_tauj_RegEmuBits_t
Content of the TAUJ0EMU: TAU Emulation Register
Members:
Rfu - Reserved for future use
Svs_Dis - Emulation control bit
*/
typedef struct {
uint8_t Res : 7;
uint8_t Svs_Dis : 1;
} r_tauj_RegEmuBits_t;
typedef union {
r_tauj_RegEmuBits_t Bits;
uint8_t Byte;
} r_tauj_RegEmu_t;
#endif /* R_TAUJ_REGS_H_ */