debug

source/Driver/Clock/Clock.c

@@ -108,6 +108,7 @@ static const r_dev_ClkSelConfig_t g_stClkSelectionCfg[] =
     {R_DEV_CKS_CPU, R_DEV_CKS_SRC_PLL0, 2, 0u},
     {R_DEV_CKS_SFMA, R_DEV_CKS_SRC_PLL0, 3, 0u},
     {R_DEV_CKS_SSIF, R_DEV_CKS_SRC_PLLFIX, 156, 0u},
+    {R_DEV_CKS_RLIN, R_DEV_CKS_SRC_PLLFIX_10, 0, 0u},
 
     /* delimiter - do not remove */
     {R_DEV_CKS_LAST, R_DEV_CKS_SRC_MOSC, 2, 0u},

source/Driver/GPIO/GPIO.c

@@ -18,8 +18,8 @@ const uint32_t g_u32GPIOConfigArray[][2U] =
     0x00010010ul,  /*Pin_P0_1 GPIO_IN SCHMITT1PDSC:L PU/PD:NULL P:L */
     0x00010010ul,  /*Pin_P0_1 GPIO_IN SCHMITT1PDSC:L PU/PD:NULL P:L */
 
-    0x00400050ul,  /*Pin_P0_2 INTP1 TTLPDSC:L PU/PD:NULL P:L */
-    0x00400050ul,  /*Pin_P0_2 INTP1 TTLPDSC:L PU/PD:NULL P:L */
+    0x00400040ul,  /*Pin_P0_2 RLIN32TX TTLPDSC:L PU/PD:NULL P:L */
+    0x00400040ul,  /*Pin_P0_2 RLIN32TX TTLPDSC:L PU/PD:NULL P:L */
 
     0x00400050ul,  /*Pin_P0_3 RLIN32RX/INTP2 TTLPDSC:L PU/PD:NULL P:L */
     0x00400050ul,  /*Pin_P0_3 RLIN32RX/INTP2 TTLPDSC:L PU/PD:NULL P:L */
@@ -150,7 +150,7 @@ const uint32_t g_u32GPIOConfigArray[][2U] =
     0x00010000ul,  /*Pin_P16_3 GPIO_OUT SCHMITT1PDSC:L PU/PD:NULL P:L */
     0x00010000ul,  /*Pin_P16_3 GPIO_OUT SCHMITT1PDSC:L PU/PD:NULL P:L */
 
-    0x00000060ul,  /*Pin_P16_4 ISM21 SCHMITT1PDSC:L PU/PD:NULL P:L */
+    0x00010000ul,  /*Pin_P16_4 GPIO_OUT SCHMITT1PDSC:L PU/PD:NULL P:L */
     0x00010000ul,  /*Pin_P16_4 GPIO_OUT SCHMITT1PDSC:L PU/PD:NULL P:L */
 
     0x00000042ul,  /*Pin_P16_5 TAUB0O11 SCHMITT1PDSC:L PU/PD:NULL P:L */

source/Driver/GPIO/GPIO.h

@@ -466,6 +466,7 @@
 #define BUZZER_MCU_OUT GPIO_OUT_PORT16_PIN01
 #define TEMP_R_LED_OUT GPIO_OUT_PORT16_PIN02
 #define TACHO_A39_OUT GPIO_OUT_PORT16_PIN03
+#define LIN_SLP_N_MCU GPIO_OUT_PORT16_PIN04
 #define WAKE_N_MCU_IN GPIO_IN_PORT16_PIN06
 #define CD4051A_A_MCU_OUT GPIO_OUT_PORT16_PIN07
 #define CD4051A_B_MCU_OUT GPIO_OUT_PORT16_PIN08

source/Driver/UART/UART.c

@@ -685,7 +685,7 @@ void TJA1021_Enable(unsigned char state)
 
     // DDRR_DDRR3 = 1;
     // PTR_PTR3 = state;
-    GPIO_OUT_PORT16_PIN04 = state;
+    LIN_SLP_N_MCU = state;
 }
 
 /*-------------------------------------------------------------------------

source/System/r_d1mx_isr.c

@@ -33,7 +33,6 @@ agreement.
 ****************************************************************************
 */
 
-
 /*******************************************************************************
   Title: r7f701412 Interrupt Functions
 
@@ -52,19 +51,19 @@ agreement.
 
 /* Include compiler specific intrinsics for synchronisation */
 #pragma ghs startnomisra
-#include "v800_ghs.h"   /* __NOP(), __SYNCP(), __SYNCM() */
+#include "v800_ghs.h" /* __NOP(), __SYNCP(), __SYNCM() */
 #pragma ghs endnomisra
 
-
-#if defined (R_DBG_PRINT_DEV_REGS) || defined (R_DBG_PRINT_MSG)
-   #include <stdio.h> 
-   #include "r_dbg_api.h"
+#if defined(R_DBG_PRINT_DEV_REGS) || defined(R_DBG_PRINT_MSG)
+#include <stdio.h>
+#include "r_dbg_api.h"
 #else
-    #define R_DBG_PRINT(lvl, txt) 
+#define R_DBG_PRINT(lvl, txt)
 #endif
 
 #ifdef USE_RLIN3
-#include "r_rlin3_api.h"
+//#include "r_rlin3_api.h"
+#include "UART.h"
 #endif
 #ifdef USE_AWOT
 #include "Sys_Tick.h"
@@ -77,11 +76,11 @@ agreement.
 #endif
 
 #ifdef USE_CSIG
- #include "r_csig_api.h"
+#include "r_csig_api.h"
 #endif
 
 #ifdef USE_CSIH
- #include "CSIH.h"
+#include "CSIH.h"
 #endif
 
 #ifdef USE_DMA
@@ -119,7 +118,7 @@ agreement.
 #endif
 
 #ifdef USE_VOCA
-#include "r_ddb_api.h"      /* display database with display timings */
+#include "r_ddb_api.h" /* display database with display timings */
 #include "r_voca_api.h"
 #endif
 
@@ -151,7 +150,7 @@ agreement.
 #endif
 
 #ifdef USE_JCUA
-    #include "r_jcua_api.h"
+#include "r_jcua_api.h"
 #endif
 
 #ifdef USE_VDCE
@@ -196,7 +195,6 @@ agreement.
 #include "Internal_Flash.h"
 #endif
 
-
 /*******************************************************************************
   Section: Synchronisation Functions
 */
@@ -237,7 +235,8 @@ void R_DEV_SyncM(void)
 float32_t R_DEV_SQRTF(float32_t val)
 {
     float32_t result;
-    asm ("sqrtf.s %0, %1" : "+r" (val),"=r" (result));
+    asm("sqrtf.s %0, %1"
+        : "+r"(val), "=r"(result));
     return result;
 }
 
@@ -245,14 +244,13 @@ float32_t R_DEV_SQRTF(float32_t val)
   Section: Interrupt Functions 
 */
 
-
 #pragma ghs startnomisra
 
 #ifdef PRIO_0_ENABLE
 #pragma ghs interrupt
-void EINTPRIO_0(void) 
+void EINTPRIO_0(void)
 {
-    asm("nop"); 
+    asm("nop");
 }
 #endif
 
@@ -261,11 +259,12 @@ void EINTPRIO_0(void)
 /**************************************************/
 
 #ifdef PIE_ENABLE
-void R_PIE_Isr( void );
+void R_PIE_Isr(void);
 
 FETRAP_EXCEPTION(PIE, loc_PIE);
 
-void loc_PIE(void) {
+void loc_PIE(void)
+{
     R_PIE_Isr();
 }
 #endif
@@ -278,59 +277,64 @@ void loc_PIE(void) {
 
 FETRAP_EXCEPTION(FEINT, loc_FEINT);
 
-void loc_FEINT(void) {
+void loc_FEINT(void)
+{
     R_ECM_FeIntIsr(0);
 }
 #endif
 
 #ifdef FENMI_ENABLE
 #pragma ghs interrupt
-void FENMI(void) {
+void FENMI(void)
+{
     R_ECM_FeNmiIsr(0);
 }
 #endif
 
-
 /**************************************************/
 /* ADC Interrupts                                */
 /**************************************************/
 
 #ifdef INTADCE0TSN_ENABLE
-#pragma ghs interrupt 
-void INTADCE0TSN(void) {
-     R_ADC_IsrTsn(0);
+#pragma ghs interrupt
+void INTADCE0TSN(void)
+{
+    R_ADC_IsrTsn(0);
 }
 #endif
 
 #ifdef INTADCE0I1_ENABLE
 #pragma ghs interrupt
-void INTADCE0I1(void) {
+void INTADCE0I1(void)
+{
     R_ADC_Isr0(0);
 }
 #endif
 
 #ifdef INTADCE0I2_ENABLE
 #pragma ghs interrupt
-void INTADCE0I2(void) {
+void INTADCE0I2(void)
+{
     R_ADC_Isr1(0);
 }
 #endif
 
 #ifdef INTADCE0I3_ENABLE
 #pragma ghs interrupt
-void INTADCE0I3(void) {
+void INTADCE0I3(void)
+{
     R_ADC_Isr2(0);
 }
 #endif
 
-
 /**************************************************/
 /* AWOT Interrupts                                */
 /**************************************************/
 
 #ifdef INTAWOT_ENABLE
 #pragma ghs interrupt
-void INTAWOT(void) {
+void INTAWOT(void)
+{
     R_AWOT_TintIsr(0);
 }
 #endif
@@ -340,8 +344,8 @@ void INTAWOT(void) {
 /**************************************************/
 
 #ifdef INTOSTM0_ENABLE
-#pragma ghs interrupt 
-void INTOSTM0(void) 
+#pragma ghs interrupt
+void INTOSTM0(void)
 {
     R_OSTM_TintIsr(0);
 }
@@ -349,7 +353,7 @@ void INTOSTM0(void)
 
 #ifdef INTOSTM1_ENABLE
 #pragma ghs interrupt
-void INTOSTM1(void) 
+void INTOSTM1(void)
 {
     R_OSTM_TintIsr(1);
 }
@@ -362,160 +366,187 @@ void INTOSTM1(void)
 /*  RLIN3 unit 0 */
 #ifdef INTRLIN30UR0_ENABLE
 #pragma ghs interrupt
-void INTRLIN30UR0(void) {
-    R_RLIN3_IsrTx(0);
+void INTRLIN30UR0(void)
+{
+   // R_RLIN3_IsrTx(0);
+    UART_CH0_TX_ISR();
 }
 #endif
 
 #ifdef INTRLIN30UR1_ENABLE
 #pragma ghs interrupt
-void INTRLIN30UR1(void) {
-    R_RLIN3_IsrRx(0);
+void INTRLIN30UR1(void)
+{
+   // R_RLIN3_IsrRx(0);
+    UART_CH0_RX_ISR();
 }
 #endif
 
 #ifdef INTRLIN30UR2_ENABLE
 #pragma ghs interrupt
-void INTRLIN30UR2(void) {
-    R_RLIN3_IsrRE(0);
+void INTRLIN30UR2(void)
+{
+   // R_RLIN3_IsrRE(0);
 }
 #endif
 
 /*  RLIN3 unit 1 */
 #ifdef INTRLIN31UR0_ENABLE
 #pragma ghs interrupt
-void INTRLIN31UR0(void) {
-    R_RLIN3_IsrTx(1);
+void INTRLIN31UR0(void)
+{
+    //R_RLIN3_IsrTx(1);
+    UART_CH1_TX_ISR();
 }
 #endif
 
 #ifdef INTRLIN31UR1_ENABLE
 #pragma ghs interrupt
-void INTRLIN31UR1(void) {
-    R_RLIN3_IsrRx(1);
+void INTRLIN31UR1(void)
+{
+    //R_RLIN3_IsrRx(1);
+     UART_CH1_RX_ISR();
 }
 #endif
 
 #ifdef INTRLIN31UR2_ENABLE
 #pragma ghs interrupt
-void INTRLIN31UR2(void) {
-    R_RLIN3_IsrRE(1);
+void INTRLIN31UR2(void)
+{
+    //R_RLIN3_IsrRE(1);
 }
 #endif
 
 /*  RLIN3 unit 2 */
 #ifdef INTRLIN32UR0_ENABLE
 #pragma ghs interrupt
-void INTRLIN32UR0(void) {
-    R_RLIN3_IsrTx(2);
+void INTRLIN32UR0(void)
+{
+    //R_RLIN3_IsrTx(2);
+     UART_CH2_TX_ISR();
 }
 #endif
 
 #ifdef INTRLIN32UR1_ENABLE
 #pragma ghs interrupt
-void INTRLIN32UR1(void) {
-    R_RLIN3_IsrRx(2);
+void INTRLIN32UR1(void)
+{
+    //R_RLIN3_IsrRx(2);
+     UART_CH2_RX_ISR();
 }
 #endif
 
 #ifdef INTRLIN32UR2_ENABLE
 #pragma ghs interrupt
-void INTRLIN32UR2(void) {
-    R_RLIN3_IsrRE(2);
+void INTRLIN32UR2(void)
+{
+    //R_RLIN3_IsrRE(2);
 }
 #endif
 
 /*  RLIN3 unit 3 */
 #ifdef INTRLIN33UR0_ENABLE
 #pragma ghs interrupt
-void INTRLIN33UR0(void) {
-    R_RLIN3_IsrTx(3);
+void INTRLIN33UR0(void)
+{
+   // R_RLIN3_IsrTx(3);
+     UART_CH3_TX_ISR();
 }
 #endif
 
 #ifdef INTRLIN33UR1_ENABLE
 #pragma ghs interrupt
-void INTRLIN33UR1(void) {
-    R_RLIN3_IsrRx(3);
+void INTRLIN33UR1(void)
+{
+    //R_RLIN3_IsrRx(3);
+     UART_CH3_RX_ISR();
 }
 #endif
 
 #ifdef INTRLIN33UR2_ENABLE
 #pragma ghs interrupt
-void INTRLIN33UR2(void) {
-    R_RLIN3_IsrRE(3);
+void INTRLIN33UR2(void)
+{
+    //R_RLIN3_IsrRE(3);
 }
 #endif
 
-
 /**************************************************/
 /* CSIG Interrupts                                */
 /**************************************************/
 
 #ifdef INTCSIG0IRE_ENABLE
 #pragma ghs interrupt
-void INTCSIG0IRE(void) {
+void INTCSIG0IRE(void)
+{
     R_CSIG_IsrTire(0);
 }
 #endif
 
 #ifdef INTCSIG0IR_ENABLE
 #pragma ghs interrupt
-void INTCSIG0IR(void) {
+void INTCSIG0IR(void)
+{
     R_CSIG_IsrTir(0);
 }
 #endif
 
 #ifdef INTCSIG0IC_ENABLE
 #pragma ghs interrupt
-void INTCSIG0IC(void) {
+void INTCSIG0IC(void)
+{
     R_CSIG_IsrTic(0);
 }
 #endif
 
 #ifdef INTCSIG1IRE_ENABLE
 #pragma ghs interrupt
-void INTCSIG1IRE(void) {
+void INTCSIG1IRE(void)
+{
     R_CSIG_IsrTire(1);
 }
 #endif
 
 #ifdef INTCSIG1IR_ENABLE
 #pragma ghs interrupt
-void INTCSIG1IR(void) {
+void INTCSIG1IR(void)
+{
     R_CSIG_IsrTir(1);
 }
 #endif
 
 #ifdef INTCSIG1IC_ENABLE
 #pragma ghs interrupt
-void INTCSIG1IC(void) {
+void INTCSIG1IC(void)
+{
     R_CSIG_IsrTic(1);
 }
 #endif
 
 #ifdef INTCSIG2IRE_ENABLE
 #pragma ghs interrupt
-void INTCSIG2IRE(void) {
+void INTCSIG2IRE(void)
+{
     R_CSIG_IsrTire(2);
 }
 #endif
 
 #ifdef INTCSIG2IR_ENABLE
 #pragma ghs interrupt
-void INTCSIG2IR(void) {
+void INTCSIG2IR(void)
+{
     R_CSIG_IsrTir(2);
 }
 #endif
 
 #ifdef INTCSIG2IC_ENABLE
 #pragma ghs interrupt
-void INTCSIG2IC(void) {
+void INTCSIG2IC(void)
+{
     R_CSIG_IsrTic(2);
 }
 #endif
 
-
 /**************************************************/
 /* ETNB Interrupts                                */
 /**************************************************/
@@ -547,62 +578,55 @@ void INTETNB0LINE3(void)
 
 #endif
 
-
-
 /**************************************************/
 /* CSIH Interrupts                                */
 /**************************************************/
 
 #ifdef USE_CSIH
 #pragma ghs interrupt
-void INTCSIH0IC (void)
+void INTCSIH0IC(void)
 {
     CSIH_Ch0_Tx_ISR();
 }
 
 #pragma ghs interrupt
-void INTCSIH0IR (void)
+void INTCSIH0IR(void)
 {
     CSIH_Ch0_Rx_ISR();
 }
 
 #pragma ghs interrupt
-void INTCSIH0IRE (void)
+void INTCSIH0IRE(void)
 {
-
 }
 
 #pragma ghs interrupt
-void INTCSIH0IJC (void)
+void INTCSIH0IJC(void)
 {
-  
 }
 
 #pragma ghs interrupt
-void INTCSIH1IC (void)
+void INTCSIH1IC(void)
 {
     CSIH_Ch1_Tx_ISR();
 }
 
 #pragma ghs interrupt
-void INTCSIH1IR (void)
+void INTCSIH1IR(void)
 {
     CSIH_Ch1_Rx_ISR();
 }
 
 #pragma ghs interrupt
-void INTCSIH1IRE (void)
+void INTCSIH1IRE(void)
 {
-
 }
 
 #pragma ghs interrupt
-void INTCSIH1IJC (void)
+void INTCSIH1IJC(void)
 {
-
 }
-#endif  /* USE_CSIH */
-
+#endif /* USE_CSIH */
 
 /**************************************************/
 /* DMA Interrupts                                 */
@@ -610,70 +634,63 @@ void INTCSIH1IJC (void)
 
 #ifdef INTDMA0_ENABLE
 #pragma ghs interrupt
-void INTDMA0(void) 
+void INTDMA0(void)
 {
     R_DMA_Isr(0, 0);
 }
 #endif
 
-
 #ifdef INTDMA1_ENABLE
 #pragma ghs interrupt
-void INTDMA1(void) 
+void INTDMA1(void)
 {
     R_DMA_Isr(0, 1);
 }
 #endif
 
-
 #ifdef INTDMA2_ENABLE
 #pragma ghs interrupt
-void INTDMA2(void) 
+void INTDMA2(void)
 {
     R_DMA_Isr(0, 2);
 }
 #endif
 
-
 #ifdef INTDMA3_ENABLE
 #pragma ghs interrupt
-void INTDMA3(void) 
+void INTDMA3(void)
 {
     R_DMA_Isr(0, 3);
 }
 #endif
 
-
 #ifdef INTDMA4_ENABLE
 #pragma ghs interrupt
-void INTDMA4(void) 
+void INTDMA4(void)
 {
     R_DMA_Isr(0, 4);
 }
 #endif
 
-
 #ifdef INTDMA5_ENABLE
 #pragma ghs interrupt
-void INTDMA5(void) 
+void INTDMA5(void)
 {
     R_DMA_Isr(0, 5);
 }
 #endif
 
-
 #ifdef INTDMA6_ENABLE
 #pragma ghs interrupt
-void INTDMA6(void) 
+void INTDMA6(void)
 {
     R_DMA_Isr(0, 6);
 }
 #endif
 
-
 #ifdef INTDMA7_ENABLE
 #pragma ghs interrupt
-void INTDMA7(void) 
+void INTDMA7(void)
 {
     R_DMA_Isr(0, 7);
 }
@@ -681,70 +698,63 @@ void INTDMA7(void)
 
 #ifdef INTDMA8_ENABLE
 #pragma ghs interrupt
-void INTDMA8(void) 
+void INTDMA8(void)
 {
     R_DMA_Isr(0, 8);
 }
 #endif
 
-
 #ifdef INTDMA9_ENABLE
 #pragma ghs interrupt
-void INTDMA9(void) 
+void INTDMA9(void)
 {
     R_DMA_Isr(0, 9);
 }
 #endif
 
-
 #ifdef INTDMA10_ENABLE
 #pragma ghs interrupt
-void INTDMA10(void) 
+void INTDMA10(void)
 {
     R_DMA_Isr(0, 10);
 }
 #endif
 
-
 #ifdef INTDMA11_ENABLE
 #pragma ghs interrupt
-void INTDMA11(void) 
+void INTDMA11(void)
 {
     R_DMA_Isr(0, 11);
 }
 #endif
 
-
 #ifdef INTDMA12_ENABLE
 #pragma ghs interrupt
-void INTDMA12(void) 
+void INTDMA12(void)
 {
     R_DMA_Isr(0, 12);
 }
 #endif
 
-
 #ifdef INTDMA13_ENABLE
 #pragma ghs interrupt
-void INTDMA13(void) 
+void INTDMA13(void)
 {
     R_DMA_Isr(0, 13);
 }
 #endif
 
-
 #ifdef INTDMA14_ENABLE
 #pragma ghs interrupt
-void INTDMA14(void) 
+void INTDMA14(void)
 {
     R_DMA_Isr(0, 14);
 }
 #endif
 
-
 #ifdef INTDMA15_ENABLE
 #pragma ghs interrupt
-void INTDMA15(void) 
+void INTDMA15(void)
 {
     R_DMA_Isr(0, 15);
 }
@@ -757,70 +767,70 @@ TAUJ  interrupts
 #ifdef USE_TAUJ
 
 #pragma ghs interrupt
-void INTTAUJ0I0(void) 
+void INTTAUJ0I0(void)
 {
-    R_TAUJ_Isr(0,(r_tauj_Interrupt_t)0); 
-} 
+    R_TAUJ_Isr(0, (r_tauj_Interrupt_t)0);
+}
 
 #pragma ghs interrupt
-void INTTAUJ0I1(void) 
+void INTTAUJ0I1(void)
 {
-    R_TAUJ_Isr(0,(r_tauj_Interrupt_t)1); 
-} 
+    R_TAUJ_Isr(0, (r_tauj_Interrupt_t)1);
+}
 #pragma ghs interrupt
-void INTTAUJ0I2(void) 
+void INTTAUJ0I2(void)
 {
-   R_TAUJ_Isr(0,(r_tauj_Interrupt_t)2); 
-} 
+    R_TAUJ_Isr(0, (r_tauj_Interrupt_t)2);
+}
 #pragma ghs interrupt
-void INTTAUJ0I3(void) 
+void INTTAUJ0I3(void)
 {
-    R_TAUJ_Isr(0,(r_tauj_Interrupt_t)3);
-} 
+    R_TAUJ_Isr(0, (r_tauj_Interrupt_t)3);
+}
 
 #pragma ghs interrupt
-void INTTAUJ1I0(void) 
+void INTTAUJ1I0(void)
 {
-    R_TAUJ_Isr(1,(r_tauj_Interrupt_t)0); 
-} 
+    R_TAUJ_Isr(1, (r_tauj_Interrupt_t)0);
+}
 
 #pragma ghs interrupt
-void INTTAUJ1I1(void) 
+void INTTAUJ1I1(void)
 {
-    R_TAUJ_Isr(1,(r_tauj_Interrupt_t)1); 
-} 
+    R_TAUJ_Isr(1, (r_tauj_Interrupt_t)1);
+}
 #pragma ghs interrupt
-void INTTAUJ1I2(void) 
+void INTTAUJ1I2(void)
 {
-   R_TAUJ_Isr(1,(r_tauj_Interrupt_t)2); 
-} 
+    R_TAUJ_Isr(1, (r_tauj_Interrupt_t)2);
+}
 #pragma ghs interrupt
-void INTTAUJ1I3(void) 
+void INTTAUJ1I3(void)
 {
-    R_TAUJ_Isr(1,(r_tauj_Interrupt_t)3);
-} 
+    R_TAUJ_Isr(1, (r_tauj_Interrupt_t)3);
+}
 
 #pragma ghs interrupt
-void INTTAUJ2I0(void) 
+void INTTAUJ2I0(void)
 {
-    R_TAUJ_Isr(2,(r_tauj_Interrupt_t)0); 
-} 
+    R_TAUJ_Isr(2, (r_tauj_Interrupt_t)0);
+}
 
 #pragma ghs interrupt
-void INTTAUJ2I1(void) 
+void INTTAUJ2I1(void)
 {
-    R_TAUJ_Isr(2,(r_tauj_Interrupt_t)1); 
-} 
+    R_TAUJ_Isr(2, (r_tauj_Interrupt_t)1);
+}
 #pragma ghs interrupt
-void INTTAUJ2I2(void) 
+void INTTAUJ2I2(void)
 {
-   R_TAUJ_Isr(2,(r_tauj_Interrupt_t)2); 
-} 
+    R_TAUJ_Isr(2, (r_tauj_Interrupt_t)2);
+}
 #pragma ghs interrupt
-void INTTAUJ2I3(void) 
+void INTTAUJ2I3(void)
 {
-    R_TAUJ_Isr(2,(r_tauj_Interrupt_t)3);
-} 
+    R_TAUJ_Isr(2, (r_tauj_Interrupt_t)3);
+}
 
 #endif
 
@@ -829,14 +839,14 @@ void INTTAUJ2I3(void)
 /**************************************************/
 #ifdef INTWDTA0_ENABLE
 #pragma ghs interrupt
-void INTWDTA0(void) 
+void INTWDTA0(void)
 {
     R_WDTA_Isr(0);
 }
 #endif
 #ifdef INTWDTA1_ENABLE
 #pragma ghs interrupt
-void INTWDTA1(void) 
+void INTWDTA1(void)
 {
     R_WDTA_Isr(1);
 }
@@ -848,7 +858,7 @@ void INTWDTA1(void)
 #ifdef USE_RTCA
 
 #pragma ghs interrupt
-void INTRTCA01S(void) 
+void INTRTCA01S(void)
 {
     R_RTCA_Isr(0, R_RTCA_INT_1S);
 }
@@ -865,7 +875,7 @@ void INTRTCA0R(void)
     R_RTCA_Isr(0, R_RTCA_INT_R);
 }
 
-#endif  /* RTCA */
+#endif /* RTCA */
 
 /**************************************************
 TAUB  interrupts 
@@ -874,297 +884,296 @@ TAUB  interrupts
 #ifdef USE_TAUB
 
 #pragma ghs interrupt
-void INTTAUB0I0(void) 
-  {
-   // R_TAUB_Isr(0,(r_taub_Interrupt_t) 0); 
-
-  } 
+void INTTAUB0I0(void)
+{
+    // R_TAUB_Isr(0,(r_taub_Interrupt_t) 0);
+}
 
 #pragma ghs interrupt
-void INTTAUB0I1(void) 
-  {
-   // R_TAUB_Isr(0,(r_taub_Interrupt_t) 1); 
-   TimerB_Overflow_Isr();
-  } 
+void INTTAUB0I1(void)
+{
+    // R_TAUB_Isr(0,(r_taub_Interrupt_t) 1);
+    TimerB_Overflow_Isr();
+}
 
 #pragma ghs interrupt
-void INTTAUB0I2(void) 
-  {
-   // R_TAUB_Isr(0,(r_taub_Interrupt_t) 2); 
-TimerB_Input_Isr(TIMERB_0_CH2);
-  } 
+void INTTAUB0I2(void)
+{
+    // R_TAUB_Isr(0,(r_taub_Interrupt_t) 2);
+    TimerB_Input_Isr(TIMERB_0_CH2);
+}
 
 #pragma ghs interrupt
-void INTTAUB0I3(void) 
-  {
-   // R_TAUB_Isr(0,(r_taub_Interrupt_t) 3); 
-  } 
+void INTTAUB0I3(void)
+{
+    // R_TAUB_Isr(0,(r_taub_Interrupt_t) 3);
+}
 
 #pragma ghs interrupt
-void INTTAUB0I4(void) 
-  {
-   // R_TAUB_Isr(0,(r_taub_Interrupt_t) 4); 
-  } 
+void INTTAUB0I4(void)
+{
+    // R_TAUB_Isr(0,(r_taub_Interrupt_t) 4);
+}
 
 #pragma ghs interrupt
-void INTTAUB0I5(void) 
-  {
-   // R_TAUB_Isr(0,(r_taub_Interrupt_t) 5); 
-  } 
+void INTTAUB0I5(void)
+{
+    // R_TAUB_Isr(0,(r_taub_Interrupt_t) 5);
+}
 
 #pragma ghs interrupt
-void INTTAUB0I6(void) 
-  {
-   // R_TAUB_Isr(0,(r_taub_Interrupt_t) 6); 
-  } 
+void INTTAUB0I6(void)
+{
+    // R_TAUB_Isr(0,(r_taub_Interrupt_t) 6);
+}
 
 #pragma ghs interrupt
-void INTTAUB0I7(void) 
-  {
-   // R_TAUB_Isr(0,(r_taub_Interrupt_t) 7); 
-  } 
+void INTTAUB0I7(void)
+{
+    // R_TAUB_Isr(0,(r_taub_Interrupt_t) 7);
+}
 
 #pragma ghs interrupt
-void INTTAUB0I8(void) 
-  {
-   // R_TAUB_Isr(0,(r_taub_Interrupt_t) 8); 
-  } 
+void INTTAUB0I8(void)
+{
+    // R_TAUB_Isr(0,(r_taub_Interrupt_t) 8);
+}
 
 #pragma ghs interrupt
-void INTTAUB0I9(void) 
-  {
-    //R_TAUB_Isr(0,(r_taub_Interrupt_t) 9); 
-//TimerB_Overflow_Isr();
-  } 
+void INTTAUB0I9(void)
+{
+    //R_TAUB_Isr(0,(r_taub_Interrupt_t) 9);
+    //TimerB_Overflow_Isr();
+}
 
 #pragma ghs interrupt
-void INTTAUB0I10(void) 
-  {
-    //R_TAUB_Isr(0,(r_taub_Interrupt_t) 10); 
-//TimerB_Input_Isr();
-  } 
+void INTTAUB0I10(void)
+{
+    //R_TAUB_Isr(0,(r_taub_Interrupt_t) 10);
+    //TimerB_Input_Isr();
+}
 
 #pragma ghs interrupt
-void INTTAUB0I11(void) 
-  {
-    //R_TAUB_Isr(0,(r_taub_Interrupt_t) 11); 
-  } 
+void INTTAUB0I11(void)
+{
+    //R_TAUB_Isr(0,(r_taub_Interrupt_t) 11);
+}
 
 #pragma ghs interrupt
-void INTTAUB0I12(void) 
-  {
-   // R_TAUB_Isr(0,(r_taub_Interrupt_t) 12); 
-  } 
+void INTTAUB0I12(void)
+{
+    // R_TAUB_Isr(0,(r_taub_Interrupt_t) 12);
+}
 
 #pragma ghs interrupt
-void INTTAUB0I13(void) 
-  {
-   // R_TAUB_Isr(0,(r_taub_Interrupt_t) 13); 
-  } 
+void INTTAUB0I13(void)
+{
+    // R_TAUB_Isr(0,(r_taub_Interrupt_t) 13);
+}
 
 #pragma ghs interrupt
-void INTTAUB0I14(void) 
-  {
-   // R_TAUB_Isr(0,(r_taub_Interrupt_t) 14); 
-  } 
+void INTTAUB0I14(void)
+{
+    // R_TAUB_Isr(0,(r_taub_Interrupt_t) 14);
+}
 
 #pragma ghs interrupt
-void INTTAUB0I15(void) 
-  {
-   // R_TAUB_Isr(0,(r_taub_Interrupt_t) 15); 
-  } 
+void INTTAUB0I15(void)
+{
+    // R_TAUB_Isr(0,(r_taub_Interrupt_t) 15);
+}
 
 #pragma ghs interrupt
-void INTTAUB1I0(void) 
-  {
-   // R_TAUB_Isr(1,(r_taub_Interrupt_t) 0); 
-  } 
+void INTTAUB1I0(void)
+{
+    // R_TAUB_Isr(1,(r_taub_Interrupt_t) 0);
+}
 
 #pragma ghs interrupt
-void INTTAUB1I1(void) 
-  {
-  //  R_TAUB_Isr(1,(r_taub_Interrupt_t) 1); 
-  } 
+void INTTAUB1I1(void)
+{
+    //  R_TAUB_Isr(1,(r_taub_Interrupt_t) 1);
+}
 
 #pragma ghs interrupt
-void INTTAUB1I2(void) 
-  {
-   // R_TAUB_Isr(1,(r_taub_Interrupt_t) 2); 
-  } 
+void INTTAUB1I2(void)
+{
+    // R_TAUB_Isr(1,(r_taub_Interrupt_t) 2);
+}
 
 #pragma ghs interrupt
-void INTTAUB1I3(void) 
-  {
-   // R_TAUB_Isr(1,(r_taub_Interrupt_t) 3); 
-  } 
+void INTTAUB1I3(void)
+{
+    // R_TAUB_Isr(1,(r_taub_Interrupt_t) 3);
+}
 
 #pragma ghs interrupt
-void INTTAUB1I4(void) 
-  {
-    //R_TAUB_Isr(1,(r_taub_Interrupt_t) 4); 
-  } 
+void INTTAUB1I4(void)
+{
+    //R_TAUB_Isr(1,(r_taub_Interrupt_t) 4);
+}
 
 #pragma ghs interrupt
-void INTTAUB1I5(void) 
-  {
-  //  R_TAUB_Isr(1,(r_taub_Interrupt_t) 5); 
-  } 
+void INTTAUB1I5(void)
+{
+    //  R_TAUB_Isr(1,(r_taub_Interrupt_t) 5);
+}
 
 #pragma ghs interrupt
-void INTTAUB1I6(void) 
-  {
-   // R_TAUB_Isr(1,(r_taub_Interrupt_t) 6); 
-  } 
+void INTTAUB1I6(void)
+{
+    // R_TAUB_Isr(1,(r_taub_Interrupt_t) 6);
+}
 
 #pragma ghs interrupt
-void INTTAUB1I7(void) 
-  {
-   // R_TAUB_Isr(1,(r_taub_Interrupt_t) 7); 
-  } 
+void INTTAUB1I7(void)
+{
+    // R_TAUB_Isr(1,(r_taub_Interrupt_t) 7);
+}
 
 #pragma ghs interrupt
-void INTTAUB1I8(void) 
-  {
-   // R_TAUB_Isr(1,(r_taub_Interrupt_t) 8); 
-  } 
+void INTTAUB1I8(void)
+{
+    // R_TAUB_Isr(1,(r_taub_Interrupt_t) 8);
+}
 
 #pragma ghs interrupt
-void INTTAUB1I9(void) 
-  {
-   // R_TAUB_Isr(1,(r_taub_Interrupt_t) 9); 
-  } 
+void INTTAUB1I9(void)
+{
+    // R_TAUB_Isr(1,(r_taub_Interrupt_t) 9);
+}
 
 #pragma ghs interrupt
-void INTTAUB1I10(void) 
-  {
-   // R_TAUB_Isr(1,(r_taub_Interrupt_t) 10); 
-  } 
+void INTTAUB1I10(void)
+{
+    // R_TAUB_Isr(1,(r_taub_Interrupt_t) 10);
+}
 
 #pragma ghs interrupt
-void INTTAUB1I11(void) 
-  {
-    //R_TAUB_Isr(1,(r_taub_Interrupt_t) 11); 
-  } 
+void INTTAUB1I11(void)
+{
+    //R_TAUB_Isr(1,(r_taub_Interrupt_t) 11);
+}
 
 #pragma ghs interrupt
-void INTTAUB1I12(void) 
-  {
-   // R_TAUB_Isr(1,(r_taub_Interrupt_t) 12); 
-  } 
+void INTTAUB1I12(void)
+{
+    // R_TAUB_Isr(1,(r_taub_Interrupt_t) 12);
+}
 
 #pragma ghs interrupt
-void INTTAUB1I13(void) 
-  {
-   // R_TAUB_Isr(1,(r_taub_Interrupt_t) 13); 
-  } 
+void INTTAUB1I13(void)
+{
+    // R_TAUB_Isr(1,(r_taub_Interrupt_t) 13);
+}
 
 #pragma ghs interrupt
-void INTTAUB1I14(void) 
-  {
-    //R_TAUB_Isr(1,(r_taub_Interrupt_t) 14); 
-  } 
+void INTTAUB1I14(void)
+{
+    //R_TAUB_Isr(1,(r_taub_Interrupt_t) 14);
+}
 
 #pragma ghs interrupt
-void INTTAUB1I15(void) 
-  {
-   // R_TAUB_Isr(1,(r_taub_Interrupt_t) 15); 
-  } 
+void INTTAUB1I15(void)
+{
+    // R_TAUB_Isr(1,(r_taub_Interrupt_t) 15);
+}
 
 #pragma ghs interrupt
-void INTTAUB2I0(void) 
-  {
-    //R_TAUB_Isr(2,(r_taub_Interrupt_t) 0); 
-  } 
+void INTTAUB2I0(void)
+{
+    //R_TAUB_Isr(2,(r_taub_Interrupt_t) 0);
+}
 
 #pragma ghs interrupt
-void INTTAUB2I1(void) 
-  {
-   // R_TAUB_Isr(2,(r_taub_Interrupt_t) 1); 
-  } 
+void INTTAUB2I1(void)
+{
+    // R_TAUB_Isr(2,(r_taub_Interrupt_t) 1);
+}
 
 #pragma ghs interrupt
-void INTTAUB2I2(void) 
-  {
-   // R_TAUB_Isr(2,(r_taub_Interrupt_t) 2); 
-  } 
+void INTTAUB2I2(void)
+{
+    // R_TAUB_Isr(2,(r_taub_Interrupt_t) 2);
+}
 
 #pragma ghs interrupt
-void INTTAUB2I3(void) 
-  {
-    //R_TAUB_Isr(2,(r_taub_Interrupt_t) 3); 
-  } 
+void INTTAUB2I3(void)
+{
+    //R_TAUB_Isr(2,(r_taub_Interrupt_t) 3);
+}
 
 #pragma ghs interrupt
-void INTTAUB2I4(void) 
-  {
-  //  R_TAUB_Isr(2,(r_taub_Interrupt_t) 4); 
-  } 
+void INTTAUB2I4(void)
+{
+    //  R_TAUB_Isr(2,(r_taub_Interrupt_t) 4);
+}
 
 #pragma ghs interrupt
-void INTTAUB2I5(void) 
-  {
-   // R_TAUB_Isr(2,(r_taub_Interrupt_t) 5); 
-  } 
+void INTTAUB2I5(void)
+{
+    // R_TAUB_Isr(2,(r_taub_Interrupt_t) 5);
+}
 
 #pragma ghs interrupt
-void INTTAUB2I6(void) 
-  {
-   // R_TAUB_Isr(2,(r_taub_Interrupt_t) 6); 
-  } 
+void INTTAUB2I6(void)
+{
+    // R_TAUB_Isr(2,(r_taub_Interrupt_t) 6);
+}
 
 #pragma ghs interrupt
-void INTTAUB2I7(void) 
-  {
-   // R_TAUB_Isr(2,(r_taub_Interrupt_t) 7); 
-  } 
+void INTTAUB2I7(void)
+{
+    // R_TAUB_Isr(2,(r_taub_Interrupt_t) 7);
+}
 
 #pragma ghs interrupt
-void INTTAUB2I8(void) 
-  {
-    //R_TAUB_Isr(2,(r_taub_Interrupt_t) 8); 
-  } 
+void INTTAUB2I8(void)
+{
+    //R_TAUB_Isr(2,(r_taub_Interrupt_t) 8);
+}
 
 #pragma ghs interrupt
-void INTTAUB2I9(void) 
-  {
-   // R_TAUB_Isr(2,(r_taub_Interrupt_t) 9); 
-  } 
+void INTTAUB2I9(void)
+{
+    // R_TAUB_Isr(2,(r_taub_Interrupt_t) 9);
+}
 
 #pragma ghs interrupt
-void INTTAUB2I10(void) 
-  {
-   // R_TAUB_Isr(2,(r_taub_Interrupt_t) 10); 
-  } 
+void INTTAUB2I10(void)
+{
+    // R_TAUB_Isr(2,(r_taub_Interrupt_t) 10);
+}
 
 #pragma ghs interrupt
-void INTTAUB2I11(void) 
-  {
-   // R_TAUB_Isr(2,(r_taub_Interrupt_t) 11); 
-  } 
+void INTTAUB2I11(void)
+{
+    // R_TAUB_Isr(2,(r_taub_Interrupt_t) 11);
+}
 
 #pragma ghs interrupt
-void INTTAUB2I12(void) 
-  {
-   // R_TAUB_Isr(2,(r_taub_Interrupt_t) 12); 
-  } 
+void INTTAUB2I12(void)
+{
+    // R_TAUB_Isr(2,(r_taub_Interrupt_t) 12);
+}
 
 #pragma ghs interrupt
-void INTTAUB2I13(void) 
-  {
-  //  R_TAUB_Isr(2,(r_taub_Interrupt_t) 13); 
-  } 
+void INTTAUB2I13(void)
+{
+    //  R_TAUB_Isr(2,(r_taub_Interrupt_t) 13);
+}
 
 #pragma ghs interrupt
-void INTTAUB2I14(void) 
-  {
-    //R_TAUB_Isr(2,(r_taub_Interrupt_t) 14); 
-  } 
+void INTTAUB2I14(void)
+{
+    //R_TAUB_Isr(2,(r_taub_Interrupt_t) 14);
+}
 
 #pragma ghs interrupt
-void INTTAUB2I15(void) 
-  {
-   // R_TAUB_Isr(2,(r_taub_Interrupt_t) 15); 
-  } 
+void INTTAUB2I15(void)
+{
+    // R_TAUB_Isr(2,(r_taub_Interrupt_t) 15);
+}
 
 #endif
 
@@ -1175,74 +1184,73 @@ GPIO (external) interrupts
 #ifdef USE_GPIO
 
 #pragma ghs interrupt
-void INTP0(void) 
+void INTP0(void)
 {
-    R_GPIO_IntIsr(0); 
-} 
+    R_GPIO_IntIsr(0);
+}
 
 #pragma ghs interrupt
-void INTP1(void) 
+void INTP1(void)
 {
-    R_GPIO_IntIsr(1); 
-} 
+    R_GPIO_IntIsr(1);
+}
 
 #pragma ghs interrupt
-void INTP2(void) 
+void INTP2(void)
 {
-    R_GPIO_IntIsr(2); 
-} 
+    R_GPIO_IntIsr(2);
+}
 
 #pragma ghs interrupt
-void INTP3(void) 
+void INTP3(void)
 {
-    R_GPIO_IntIsr(3); 
-} 
+    R_GPIO_IntIsr(3);
+}
 
 #pragma ghs interrupt
-void INTP4(void) 
+void INTP4(void)
 {
-    R_GPIO_IntIsr(4); 
-} 
+    R_GPIO_IntIsr(4);
+}
 
 #pragma ghs interrupt
-void INTP5(void) 
+void INTP5(void)
 {
-    R_GPIO_IntIsr(5); 
-} 
+    R_GPIO_IntIsr(5);
+}
 
 #pragma ghs interrupt
-void INTP6(void) 
+void INTP6(void)
 {
-    R_GPIO_IntIsr(6); 
-} 
+    R_GPIO_IntIsr(6);
+}
 
 #pragma ghs interrupt
-void INTP7(void) 
+void INTP7(void)
 {
-    R_GPIO_IntIsr(7); 
-} 
+    R_GPIO_IntIsr(7);
+}
 
 #pragma ghs interrupt
-void INTP8(void) 
+void INTP8(void)
 {
-    R_GPIO_IntIsr(8); 
-} 
+    R_GPIO_IntIsr(8);
+}
 
 #pragma ghs interrupt
-void INTP9(void) 
+void INTP9(void)
 {
-    R_GPIO_IntIsr(9); 
-} 
+    R_GPIO_IntIsr(9);
+}
 
 #pragma ghs interrupt
-void INTP10(void) 
+void INTP10(void)
 {
-    R_GPIO_IntIsr(10); 
-} 
+    R_GPIO_IntIsr(10);
+}
 
 #endif
 
-
 /**************************************************/
 /* pcmp - PCM-PWM Interrupts                      */
 /**************************************************/
@@ -1250,7 +1258,7 @@ void INTP10(void)
 #ifdef USE_PCMP
 
 #pragma ghs interrupt
-void INTPCMP0FFIL(void) 
+void INTPCMP0FFIL(void)
 {
     R_PCMP_Isr(0, R_PCMP_INT_FFIL);
 }
@@ -1261,8 +1269,7 @@ void INTPCMP0FERR(void)
     R_PCMP_Isr(0, R_PCMP_INT_ERR);
 }
 
-#endif  /* PCMP */
-
+#endif /* PCMP */
 
 /**************************************************/
 /* sg - SG Interrupts                             */
@@ -1299,8 +1306,7 @@ void INTSG4TI(void)
 {
     R_SG_Isr(4);
 }
-#endif  /* SG */
-
+#endif /* SG */
 
 /**************************************************/
 /* ssif - SSIF Interrupts                         */
@@ -1341,11 +1347,10 @@ void INTSSIF1RX(void)
 #pragma ghs interrupt
 void INTSSIF1TX(void)
 {
-   /* R_SSIF_IsrTX(1);*/
-//     I2S_MAX98357_TX();
+    /* R_SSIF_IsrTX(1);*/
+    //     I2S_MAX98357_TX();
 }
-#endif  /* SSIF */
-
+#endif /* SSIF */
 
 /**************************************************/
 /* gfx - VRAM Interrupts                          */
@@ -1353,7 +1358,8 @@ void INTSSIF1TX(void)
 
 #ifdef INTVRAM_ENABLE
 #pragma ghs interrupt
-void INTVRAM_CH0_1BIT(void) {
+void INTVRAM_CH0_1BIT(void)
+{
 #ifdef USE_ROS
     R_OS_Prv_EnterInterrupt();
 #endif
@@ -1364,7 +1370,8 @@ void INTVRAM_CH0_1BIT(void) {
 }
 
 #pragma ghs interrupt
-void INTVRAM_CH0_2BIT(void) {
+void INTVRAM_CH0_2BIT(void)
+{
 #ifdef USE_ROS
     R_OS_Prv_EnterInterrupt();
 #endif
@@ -1375,7 +1382,8 @@ void INTVRAM_CH0_2BIT(void) {
 }
 
 #pragma ghs interrupt
-void INTVRAM_CH0_OVF(void) {
+void INTVRAM_CH0_OVF(void)
+{
 #ifdef USE_ROS
     R_OS_Prv_EnterInterrupt();
 #endif
@@ -1386,7 +1394,8 @@ void INTVRAM_CH0_OVF(void) {
 }
 
 #pragma ghs interrupt
-void INTVRAM_CH1_1BIT(void) {
+void INTVRAM_CH1_1BIT(void)
+{
 #ifdef USE_ROS
     R_OS_Prv_EnterInterrupt();
 #endif
@@ -1397,7 +1406,8 @@ void INTVRAM_CH1_1BIT(void) {
 }
 
 #pragma ghs interrupt
-void INTVRAM_CH1_2BIT(void) {
+void INTVRAM_CH1_2BIT(void)
+{
 #ifdef USE_ROS
     R_OS_Prv_EnterInterrupt();
 #endif
@@ -1408,7 +1418,8 @@ void INTVRAM_CH1_2BIT(void) {
 }
 
 #pragma ghs interrupt
-void INTVRAM_CH1_OVF(void) {
+void INTVRAM_CH1_OVF(void)
+{
 #ifdef USE_ROS
     R_OS_Prv_EnterInterrupt();
 #endif
@@ -1419,8 +1430,6 @@ void INTVRAM_CH1_OVF(void) {
 }
 #endif
 
-
-
 /**************************************************/
 /* gfx - LCBI Interrupts                          */
 /**************************************************/
@@ -1463,16 +1472,15 @@ void INTLCBI03QTR(void)
 }
 #endif /* USE_LCBI */
 
-
 /**************************************************/
 /* gfx - VDCE Interrupts                          */
 /**************************************************/
 
-
-#ifdef INTVDCE_ENABLE  /* USE_VDCE */
+#ifdef INTVDCE_ENABLE /* USE_VDCE */
 
 #pragma ghs interrupt
-void INTVDCE_CH0_ERR(void) {
+void INTVDCE_CH0_ERR(void)
+{
 #ifdef USE_ROS
     R_OS_Prv_EnterInterrupt();
 #endif
@@ -1484,18 +1492,20 @@ void INTVDCE_CH0_ERR(void) {
 }
 
 #pragma ghs interrupt
-void INTVDCE_CH0_GR3VBLANK(void) {
+void INTVDCE_CH0_GR3VBLANK(void)
+{
 #ifdef USE_ROS
     R_OS_Prv_EnterInterrupt();
 #endif
-    R_VDCE_Isr(0, R_VDCE_INTC_VBLANK_DELAY);    /* R_VDCE_INTC_VBLANK_DELAY ? */
+    R_VDCE_Isr(0, R_VDCE_INTC_VBLANK_DELAY); /* R_VDCE_INTC_VBLANK_DELAY ? */
 #ifdef USE_ROS
     R_OS_Prv_LeaveInterrupt();
 #endif
 }
 
 #pragma ghs interrupt
-void INTVDCE_CH0_S0VIVSYNC(void) {
+void INTVDCE_CH0_S0VIVSYNC(void)
+{
 #ifdef USE_ROS
     R_OS_Prv_EnterInterrupt();
 #endif
@@ -1506,7 +1516,8 @@ void INTVDCE_CH0_S0VIVSYNC(void) {
 }
 
 #pragma ghs interrupt
-void INTVDCE_CH0_S0LOVSYNC(void) {
+void INTVDCE_CH0_S0LOVSYNC(void)
+{
 #ifdef USE_ROS
     R_OS_Prv_EnterInterrupt();
 #endif
@@ -1517,7 +1528,8 @@ void INTVDCE_CH0_S0LOVSYNC(void) {
 }
 
 #pragma ghs interrupt
-void INTVDCE_CH0_GR3VLINE(void) {
+void INTVDCE_CH0_GR3VLINE(void)
+{
 #ifdef USE_ROS
     R_OS_Prv_EnterInterrupt();
 #endif
@@ -1528,7 +1540,8 @@ void INTVDCE_CH0_GR3VLINE(void) {
 }
 
 #pragma ghs interrupt
-void INTVDCE_CH0_S0VFIELD(void) {
+void INTVDCE_CH0_S0VFIELD(void)
+{
 #ifdef USE_ROS
     R_OS_Prv_EnterInterrupt();
 #endif
@@ -1539,7 +1552,8 @@ void INTVDCE_CH0_S0VFIELD(void) {
 }
 
 #pragma ghs interrupt
-void INTVDCE_CH0_S1LOVSYNC(void) {
+void INTVDCE_CH0_S1LOVSYNC(void)
+{
 #ifdef USE_ROS
     R_OS_Prv_EnterInterrupt();
 #endif
@@ -1550,7 +1564,8 @@ void INTVDCE_CH0_S1LOVSYNC(void) {
 }
 
 #pragma ghs interrupt
-void INTVDCE_CH0_OIRVIVSYNC(void) {
+void INTVDCE_CH0_OIRVIVSYNC(void)
+{
 #ifdef USE_ROS
     R_OS_Prv_EnterInterrupt();
 #endif
@@ -1561,7 +1576,8 @@ void INTVDCE_CH0_OIRVIVSYNC(void) {
 }
 
 #pragma ghs interrupt
-void INTVDCE_CH0_OIRLOVSYNC(void) {
+void INTVDCE_CH0_OIRLOVSYNC(void)
+{
 #ifdef USE_ROS
     R_OS_Prv_EnterInterrupt();
 #endif
@@ -1572,7 +1588,8 @@ void INTVDCE_CH0_OIRLOVSYNC(void) {
 }
 
 #pragma ghs interrupt
-void INTVDCE_CH0_OIRVLINE(void) {
+void INTVDCE_CH0_OIRVLINE(void)
+{
 #ifdef USE_ROS
     R_OS_Prv_EnterInterrupt();
 #endif
@@ -1583,7 +1600,8 @@ void INTVDCE_CH0_OIRVLINE(void) {
 }
 
 #pragma ghs interrupt
-void INTVDCE_CH1_ERR(void) {
+void INTVDCE_CH1_ERR(void)
+{
 #ifdef USE_ROS
     R_OS_Prv_EnterInterrupt();
 #endif
@@ -1594,7 +1612,8 @@ void INTVDCE_CH1_ERR(void) {
 }
 
 #pragma ghs interrupt
-void INTVDCE_CH1_GR3VBLANK(void) {
+void INTVDCE_CH1_GR3VBLANK(void)
+{
 #ifdef USE_ROS
     R_OS_Prv_EnterInterrupt();
 #endif
@@ -1605,7 +1624,8 @@ void INTVDCE_CH1_GR3VBLANK(void) {
 }
 
 #pragma ghs interrupt
-void INTVDCE_CH1_S0VIVSYNC(void) {
+void INTVDCE_CH1_S0VIVSYNC(void)
+{
 #ifdef USE_ROS
     R_OS_Prv_EnterInterrupt();
 #endif
@@ -1616,7 +1636,8 @@ void INTVDCE_CH1_S0VIVSYNC(void) {
 }
 
 #pragma ghs interrupt
-void INTVDCE_CH1_S0LOVSYNC(void) {
+void INTVDCE_CH1_S0LOVSYNC(void)
+{
 #ifdef USE_ROS
     R_OS_Prv_EnterInterrupt();
 #endif
@@ -1627,7 +1648,8 @@ void INTVDCE_CH1_S0LOVSYNC(void) {
 }
 
 #pragma ghs interrupt
-void INTVDCE_CH1_GR3VLINE(void) {
+void INTVDCE_CH1_GR3VLINE(void)
+{
 #ifdef USE_ROS
     R_OS_Prv_EnterInterrupt();
 #endif
@@ -1638,7 +1660,8 @@ void INTVDCE_CH1_GR3VLINE(void) {
 }
 
 #pragma ghs interrupt
-void INTVDCE_CH1_S0VFIELD(void) {
+void INTVDCE_CH1_S0VFIELD(void)
+{
 #ifdef USE_ROS
     R_OS_Prv_EnterInterrupt();
 #endif
@@ -1649,7 +1672,8 @@ void INTVDCE_CH1_S0VFIELD(void) {
 }
 
 #pragma ghs interrupt
-void INTVDCE_CH1_S1LOVSYNC(void) {
+void INTVDCE_CH1_S1LOVSYNC(void)
+{
 #ifdef USE_ROS
     R_OS_Prv_EnterInterrupt();
 #endif
@@ -1659,8 +1683,7 @@ void INTVDCE_CH1_S1LOVSYNC(void) {
 #endif
 }
 
-#endif  /* INTVDCE_ENABLE / USE_VDCE */
-
+#endif /* INTVDCE_ENABLE / USE_VDCE */
 
 /**************************************************/
 /* gfx - VOWE Interrupts                          */
@@ -1668,7 +1691,8 @@ void INTVDCE_CH1_S1LOVSYNC(void) {
 
 #ifdef INTVOWE_ENABLE
 #pragma ghs interrupt
-void INTVOWE(void) {
+void INTVOWE(void)
+{
 #ifdef USE_ROS
     R_OS_Prv_EnterInterrupt();
 #endif
@@ -1679,14 +1703,14 @@ void INTVOWE(void) {
 }
 #endif
 
-
 /**************************************************/
 /* gfx - MIPI Interrupts                          */
 /**************************************************/
 
 #ifdef INTMIPI0OVF_ENABLE
 #pragma ghs interrupt
-void INTMIPI0OVF(void) {
+void INTMIPI0OVF(void)
+{
 #ifdef USE_ROS
     R_OS_Prv_EnterInterrupt();
 #endif
@@ -1699,7 +1723,8 @@ void INTMIPI0OVF(void) {
 
 #ifdef INTMIPI0CTL_ENABLE
 #pragma ghs interrupt
-void INTMIPI0CTL(void) {
+void INTMIPI0CTL(void)
+{
 #ifdef USE_ROS
     R_OS_Prv_EnterInterrupt();
 #endif
@@ -1710,14 +1735,14 @@ void INTMIPI0CTL(void) {
 }
 #endif
 
-
 /**************************************************/
 /* gfx - VOCA Interrupts                         */
 /**************************************************/
 
 #ifdef INTVOCA_VOCINT_ENABLE
 #pragma ghs interrupt
-void INTVOCA_VOCINT(void) {
+void INTVOCA_VOCINT(void)
+{
 #ifdef USE_ROS
     R_OS_Prv_EnterInterrupt();
 #endif
@@ -1730,7 +1755,8 @@ void INTVOCA_VOCINT(void) {
 
 #ifdef INTVOCA_ACTMONINT_ENABLE
 #pragma ghs interrupt
-void INTVOCA_ACTMONINT(void) {
+void INTVOCA_ACTMONINT(void)
+{
 #ifdef USE_ROS
     R_OS_Prv_EnterInterrupt();
 #endif
@@ -1741,14 +1767,14 @@ void INTVOCA_ACTMONINT(void) {
 }
 #endif
 
-
 /**************************************************/
 /* gfx - DISCOM Interrupts                        */
 /**************************************************/
 
 #ifdef INTDISCOM_CMPI0_ENABLE
 #pragma ghs interrupt
-void INTDISCOM_CMPI0(void) {
+void INTDISCOM_CMPI0(void)
+{
 #ifdef USE_ROS
     R_OS_Prv_EnterInterrupt();
 #endif
@@ -1761,7 +1787,8 @@ void INTDISCOM_CMPI0(void) {
 
 #ifdef INTDISCOM_CMPI1_ENABLE
 #pragma ghs interrupt
-void INTDISCOM_CMPI1(void) {
+void INTDISCOM_CMPI1(void)
+{
 #ifdef USE_ROS
     R_OS_Prv_EnterInterrupt();
 #endif
@@ -1772,14 +1799,14 @@ void INTDISCOM_CMPI1(void) {
 }
 #endif
 
-
 /**************************************************/
 /* JCUA Interrupts                                 */
 /**************************************************/
 
 #ifdef INTJCU0EDI_ENABLE
 #pragma ghs interrupt
-void INTJCU0EDI(void) {
+void INTJCU0EDI(void)
+{
 #ifdef USE_ROS
     R_OS_Prv_EnterInterrupt();
 #endif
@@ -1792,7 +1819,8 @@ void INTJCU0EDI(void) {
 
 #ifdef INTJCU0DTI_ENABLE
 #pragma ghs interrupt
-void INTJCU0DTI(void) {
+void INTJCU0DTI(void)
+{
 #ifdef USE_ROS
     R_OS_Prv_EnterInterrupt();
 #endif
@@ -1801,8 +1829,7 @@ void INTJCU0DTI(void) {
     R_OS_Prv_LeaveInterrupt();
 #endif
 }
-#endif   
-
+#endif
 
 /**************************************************/
 /* gfx - dhd Interrupts                        */
@@ -1810,7 +1837,8 @@ void INTJCU0DTI(void) {
 
 #ifdef INTDHD_ENABLE
 #pragma ghs interrupt
-void INTDHD_SYNC(void) {
+void INTDHD_SYNC(void)
+{
 #ifdef USE_ROS
     R_OS_Prv_EnterInterrupt();
 #endif
@@ -1821,7 +1849,8 @@ void INTDHD_SYNC(void) {
 }
 
 #pragma ghs interrupt
-void INTDHD_PAUSE(void) {
+void INTDHD_PAUSE(void)
+{
 #ifdef USE_ROS
     R_OS_Prv_EnterInterrupt();
 #endif
@@ -1832,7 +1861,8 @@ void INTDHD_PAUSE(void) {
 }
 
 #pragma ghs interrupt
-void INTDHD_SPECIAL(void) {
+void INTDHD_SPECIAL(void)
+{
 #ifdef USE_ROS
     R_OS_Prv_EnterInterrupt();
 #endif
@@ -1844,7 +1874,6 @@ void INTDHD_SPECIAL(void) {
 
 #endif
 
-
 /**************************************************/
 /* ISM Interrupts                                 */
 /**************************************************/
@@ -1852,7 +1881,8 @@ void INTDHD_SPECIAL(void) {
 /*  ISM unit 0 */
 #ifdef INTISM0REACHED_ENABLE
 #pragma ghs interrupt
-void INTISM0REACHED(void) {
+void INTISM0REACHED(void)
+{
 #ifdef USE_ROS
     R_OS_Prv_EnterInterrupt();
 #endif
@@ -1865,7 +1895,8 @@ void INTISM0REACHED(void) {
 
 #ifdef INTISM0DONE_ENABLE
 #pragma ghs interrupt
-void INTISM0DONE(void) {
+void INTISM0DONE(void)
+{
 #ifdef USE_ROS
     R_OS_Prv_EnterInterrupt();
 #endif
@@ -1878,7 +1909,8 @@ void INTISM0DONE(void) {
 
 #ifdef INTISM0ZPDAD_ENABLE
 #pragma ghs interrupt
-void INTISM0ZPDAD(void) {
+void INTISM0ZPDAD(void)
+{
 #ifdef USE_ROS
     R_OS_Prv_EnterInterrupt();
 #endif
@@ -1891,7 +1923,8 @@ void INTISM0ZPDAD(void) {
 
 #ifdef INTISM0ZPD_ENABLE
 #pragma ghs interrupt
-void INTISM0ZPD(void) {
+void INTISM0ZPD(void)
+{
 #ifdef USE_ROS
     R_OS_Prv_EnterInterrupt();
 #endif
@@ -1902,7 +1935,6 @@ void INTISM0ZPD(void) {
 }
 #endif
 
-
 /**************************************************/
 /* rscan0 - RSCAN0 Interrupts                     */
 /**************************************************/
@@ -1911,15 +1943,14 @@ void INTISM0ZPD(void) {
 
 #ifdef INTRCANGERR_ENABLE
 #pragma ghs interrupt
-void INTRCANGERR(void) 
+void INTRCANGERR(void)
 {
-
 }
 #endif
 
 #ifdef INTRCANGRECC_ENABLE
 #pragma ghs interrupt
-void INTRCANGRECC(void) 
+void INTRCANGRECC(void)
 {
     //RSCAN0_FIFO_Rx_ISR();
 }
@@ -1927,7 +1958,7 @@ void INTRCANGRECC(void)
 
 #ifdef INTRCAN0ERR_ENABLE
 #pragma ghs interrupt
-void INTRCAN0ERR(void) 
+void INTRCAN0ERR(void)
 {
     RSCAN0_CH0_Err_ISR();
 }
@@ -1935,7 +1966,7 @@ void INTRCAN0ERR(void)
 
 #ifdef INTRCAN0REC_ENABLE
 #pragma ghs interrupt
-void INTRCAN0REC(void) 
+void INTRCAN0REC(void)
 {
     RSCAN0_CH0_Rx_ISR();
 }
@@ -1943,7 +1974,7 @@ void INTRCAN0REC(void)
 
 #ifdef INTRCAN0TRX_ENABLE
 #pragma ghs interrupt
-void INTRCAN0TRX(void) 
+void INTRCAN0TRX(void)
 {
     RSCAN0_CH0_Tx_ISR();
 }
@@ -1951,7 +1982,7 @@ void INTRCAN0TRX(void)
 
 #ifdef INTRCAN1ERR_ENABLE
 #pragma ghs interrupt
-void INTRCAN1ERR(void) 
+void INTRCAN1ERR(void)
 {
     RSCAN0_CH1_Err_ISR();
 }
@@ -1959,7 +1990,7 @@ void INTRCAN1ERR(void)
 
 #ifdef INTRCAN1REC_ENABLE
 #pragma ghs interrupt
-void INTRCAN1REC(void) 
+void INTRCAN1REC(void)
 {
     RSCAN0_CH1_Rx_ISR();
 }
@@ -1967,7 +1998,7 @@ void INTRCAN1REC(void)
 
 #ifdef INTRCAN1TRX_ENABLE
 #pragma ghs interrupt
-void INTRCAN1TRX(void) 
+void INTRCAN1TRX(void)
 {
     RSCAN0_CH1_Tx_ISR();
 }
@@ -1975,7 +2006,7 @@ void INTRCAN1TRX(void)
 
 #ifdef INTRCAN2ERR_ENABLE
 #pragma ghs interrupt
-void INTRCAN2ERR(void) 
+void INTRCAN2ERR(void)
 {
     RSCAN0_CH2_Err_ISR();
 }
@@ -1983,7 +2014,7 @@ void INTRCAN2ERR(void)
 
 #ifdef INTRCAN2REC_ENABLE
 #pragma ghs interrupt
-void INTRCAN2REC(void) 
+void INTRCAN2REC(void)
 {
     RSCAN0_CH2_Rx_ISR();
 }
@@ -1991,7 +2022,7 @@ void INTRCAN2REC(void)
 
 #ifdef INTRCAN2TRX_ENABLE
 #pragma ghs interrupt
-void INTRCAN2TRX(void) 
+void INTRCAN2TRX(void)
 {
     RSCAN0_CH2_Tx_ISR();
 }
@@ -2009,7 +2040,6 @@ void INTRCAN2TRX(void)
 #pragma ghs interrupt
 void INTFLERR(void)
 {
-
 }
 #endif
 
@@ -2022,12 +2052,4 @@ void INTFLENDNM(void)
 #endif
 #endif /* USE_INT_FLASH */
 
-
-
-
-
-
-
-
-
 #pragma ghs endnomisra

source/System/sys_scheduler.c

@@ -3,8 +3,6 @@
 #include "init.h"
 #include "Sys_Scheduler.h"
 #include "Sys_Tick.h"
-#include "kwp2000_tp.h"
-#include "kwp2000_protocol.h"
 
 typedef struct
 {
@@ -27,9 +25,6 @@ Sys_Scheduling_st_t   SysScheduling;
 static void Sys_Exact_50us_Task_Handler(void);
 static void Sys_Exact_100ms_Task_Handler(void);
 
-static uint8_t u08_1ms_count;
-
-
 void Sys_Init(void)
 {
     SysScheduling.msRocBak            =  0U;
@@ -102,16 +97,6 @@ void Sys_Scheduling_Service(void)
 static void Sys_Exact_50us_Task_Handler(void)
 {
     Sys_Exact_50us_Tasks();
-
-    /*----K_Line----*/
-    u08_1ms_count ++;
-    if (u08_1ms_count >= 20)
-    {
-        u08_1ms_count = 0;
-        Kwp2000_ComInit_Handle();
-        Kwp2000_Handle(); /* qitiancun */
-        Kwp2000_Timeout();
-    }
 }
 
 

source/System/tasks.c

@@ -86,6 +86,11 @@
 #include "Buzzer.h"
 #include "CAN_FUNC.h"
 
+#include "kwp2000_tp.h"
+#include "kwp2000_protocol.h"
+
+static uint8_t u08_1ms_count;
+
 /*******************************************************************************
  *                                                                              *
  *   系统常规运行模式(SYS_MODE_OFF / SYS_MODE_ON / SYS_MODE_STANDBY )任务列表   *
@@ -270,6 +275,16 @@ void Sys_Exact_50us_Tasks(void)
         SEG_LCD_Window_Control_Service();
     }
     Buzzer_Play_ISR();
+
+    /*----K_Line----*/
+    u08_1ms_count ++;
+    if (u08_1ms_count >= 20)
+    {
+        u08_1ms_count = 0;
+        Kwp2000_ComInit_Handle();
+        Kwp2000_Handle(); /* qitiancun */
+        Kwp2000_Timeout();
+    }
 }
 /*============================================================================*/
 

utility/GPIO/GPIO.c

 #include "r_typedefs.h"
+#include "dr7f701441.dvf.h"
 #include "GPIO.h"
 
 #define GPIO_STB_PROTECTED_WRITE(preg, pstatus, reg, value) \
@@ -18,8 +19,8 @@ const uint32_t g_u32GPIOConfigArray[][2U] =
     0x00010010ul,  /*Pin_P0_1 GPIO_IN SCHMITT1PDSC:L PU/PD:NULL P:L */
     0x00010010ul,  /*Pin_P0_1 GPIO_IN SCHMITT1PDSC:L PU/PD:NULL P:L */
 
-    0x00400050ul,  /*Pin_P0_2 INTP1 TTLPDSC:L PU/PD:NULL P:L */
-    0x00400050ul,  /*Pin_P0_2 INTP1 TTLPDSC:L PU/PD:NULL P:L */
+    0x00400040ul,  /*Pin_P0_2 RLIN32TX TTLPDSC:L PU/PD:NULL P:L */
+    0x00400040ul,  /*Pin_P0_2 RLIN32TX TTLPDSC:L PU/PD:NULL P:L */
 
     0x00400050ul,  /*Pin_P0_3 RLIN32RX/INTP2 TTLPDSC:L PU/PD:NULL P:L */
     0x00400050ul,  /*Pin_P0_3 RLIN32RX/INTP2 TTLPDSC:L PU/PD:NULL P:L */
@@ -150,7 +151,7 @@ const uint32_t g_u32GPIOConfigArray[][2U] =
     0x00010000ul,  /*Pin_P16_3 GPIO_OUT SCHMITT1PDSC:L PU/PD:NULL P:L */
     0x00010000ul,  /*Pin_P16_3 GPIO_OUT SCHMITT1PDSC:L PU/PD:NULL P:L */
 
-    0x00000060ul,  /*Pin_P16_4 ISM21 SCHMITT1PDSC:L PU/PD:NULL P:L */
+    0x00010000ul,  /*Pin_P16_4 GPIO_OUT SCHMITT1PDSC:L PU/PD:NULL P:L */
     0x00010000ul,  /*Pin_P16_4 GPIO_OUT SCHMITT1PDSC:L PU/PD:NULL P:L */
 
     0x00000042ul,  /*Pin_P16_5 TAUB0O11 SCHMITT1PDSC:L PU/PD:NULL P:L */

utility/GPIO/GPIO.h

 #ifndef GPIO_H__
 #define GPIO_H__
-#include "dr7f701441.dvf.h"
 
 /* --- PORT  Data Direction --- */
 #define GPIO_DIR_PORT00_PIN00 PORT_AWOPM0_0
@@ -465,6 +464,7 @@
 #define BUZZER_MCU_OUT GPIO_OUT_PORT16_PIN01
 #define TEMP_R_LED_OUT GPIO_OUT_PORT16_PIN02
 #define TACHO_A39_OUT GPIO_OUT_PORT16_PIN03
+#define LIN_SLP_N_MCU GPIO_OUT_PORT16_PIN04
 #define WAKE_N_MCU_IN GPIO_IN_PORT16_PIN06
 #define CD4051A_A_MCU_OUT GPIO_OUT_PORT16_PIN07
 #define CD4051A_B_MCU_OUT GPIO_OUT_PORT16_PIN08