Skip to content

V
VC66_7C
Commit f3345a2c authored by hu's avatar hu
Browse files
Options

更改了RTC时间停止，以及里程大计异常问题

parent e94bb947
Hide whitespace changes
Inline Side-by-side
Showing with 24228 additions and 24124 deletions
ghs/project
View file @ f3345a2c
No preview for this file type
ghs/project.hex
View file @ f3345a2c
This source diff could not be displayed because it is too large. You can view the blob instead.
ghs/project.siz
View file @ f3345a2c
project .intvect 1536
project .text 316700
project .rodata 411095
project .text 317548
project .rodata 411087
project .secinfo 120
project .syscall 6
project .romdata 9029
......
source/Application/RTE/RTE_TIME.c
View file @ f3345a2c
......@@ -14,12 +14,12 @@ void RTE_RTC_KL30_Init(void)
void RTE_RTC_Wakeup_Init(void)
{
RTC_Init();
//RTC_Init();
}
void RTE_RTC_Services_100Ms_Cbk(void)
{
RTC_Timing_Service();
RTC_Get_Time();
}
......@@ -65,7 +65,7 @@ void RTE_RTC_Confirm_Overwrite(void)
mTimmerSetting.u8RTCMinute = RTE_RTC_MINUTE; /*0~~59 in Dec*/
mTimmerSetting.u8RTCSecond = RTE_RTC_SECOND; /*0~~59 in Dec*/
RTC_Set_Time(&mTimmerSetting);
RTC_Set_Time(mTimmerSetting.u8RTCYear, mTimmerSetting.u8RTCMonth, mTimmerSetting.u8RTCDayOfMonth, mTimmerSetting.u8RTCHour, mTimmerSetting.u8RTCMinute, mTimmerSetting.u8RTCSecond);
}
......@@ -103,4 +103,4 @@ uint8_t Get_RTC_SECOND(void)
uint8_t Get_RTC_WEEK(void)
{
return RTC_WEEK ;
}
\ No newline at end of file
}
source/Driver/Clock/Clock.c
View file @ f3345a2c
#include "r_typedefs.h"
#include "dr7f701441.dvf.h"
#include "r_dev_clk_types.h"
#include "r_dev_api.h"
#include "Clock.h"
#include "GPIO.h"
#include "Watchdog.h"
#define CLOCK_PROTECTED_WRITE(preg, pstatus, reg, value) \
do \
{ \
(preg) = 0xA5U; \
(reg) = (value); \
(reg) = ~(value); \
(reg) = (value); \
} while ((pstatus) == 1U)
static const r_dev_ClkGenConfig_t g_stClockGenCfg =
{
/*mainosc*/
{
/* FrequencyHz */ R_DEV_MOSC_FRQ_HZ,
/* StabiTimeNs */ 400000UL,
/* Gain */ 3U,
/* Running */ 1U,
/* StpReqMsk */ 1U,
},
/*subosc*/
{
/* FrequencyHz */ 32768UL,
/* Running */ 0U,
/* StpReqMsk */ 0U,
},
/* PLL */
{
/*PLL0*/
{
/* Mode */ R_DEV_PLL_SSCG,
/* DithMode */ R_DEV_PLL_DITH_DOWN,
/* DithRange */ 3U,
/* ModFreq */ 50UL,
/* FrequencyHz */ 480UL * 1000UL * 1000UL,
/* StabiTimeNs */ 40000UL,
/* StpReqMsk */ 0U,
},
/*PLL1*/
{
/* Mode */ R_DEV_PLL_ON,
/* DithMode */ R_DEV_PLL_DITH_FIXED,
/* DithRange */ 0U,
/* ModFreq */ 0UL,
/* FrequencyHz */ 480UL * 1000UL * 1000UL,
/* StabiTimeNs */ 40000UL,
/* StpReqMsk */ 0U,
},
/*PLL2*/
{
/* Mode */ R_DEV_PLL_OFF,
/* DithMode */ R_DEV_PLL_DITH_FIXED,
/* DithRange */ 0U,
/* ModFreq */ 0UL,
/* FrequencyHz */ 0UL,
/* StabiTimeNs */ 0UL,
/* StpReqMsk */ 0U,
},
},
/* ROSC */
/* RoscStpReqMsk */ 1U,
/* BusEnable */
{
/* R_DEV_CLK_PLL0 */ 1U,
/* R_DEV_CLK_PLL1 */ 1U,
/* R_DEV_CLK_PLL2 */ 0U,
/* R_DEV_CLK_PLL0PIX */ 1U,
/* R_DEV_CLK_SDRB */ 1U,
/* R_DEV_CLK_ETNBP */ 1U,
/* R_DEV_CLK_MLBP */ 1U,
/* R_DEV_CLK_RSCANP */ 1U,
/* R_DEV_CLK_XCC */ 1U,
/* R_DEV_CLK_ETNBXCC */ 1U,
/* R_DEV_CLK_MLBXCC */ 1U,
},
};
static const r_dev_ClkSelConfig_t g_stClkSelectionCfg[] =
/* Cks SrcId Div StpReqMsk */
{
/* {R_DEV_CKS_RSCAN, R_DEV_CKS_SRC_PLLFIX, } */
{R_DEV_CKS_RSCANXIN, R_DEV_CKS_SRC_MOSC, 1, 0u},
{R_DEV_CKS_WDT0, R_DEV_CKS_SRC_LRNG, 256, 0u},
{R_DEV_CKS_RTC, R_DEV_CKS_SRC_MOSC, 2, 0u},
{R_DEV_CKS_OSTM, R_DEV_CKS_SRC_MOSC, 2, 0u},
{R_DEV_CKS_CLKJIT, R_DEV_CKS_SRC_DIV, 6, 0u},
{R_DEV_CKS_PLLFIX, R_DEV_CKS_SRC_PLL1, 1, 0u},
{R_DEV_CKS_CLKFIX, R_DEV_CKS_SRC_DIV, 6, 0u},
{R_DEV_CKS_CPU, R_DEV_CKS_SRC_PLL0, 2, 0u},
{R_DEV_CKS_SFMA, R_DEV_CKS_SRC_PLL0, 3, 0u},
{R_DEV_CKS_SSIF, R_DEV_CKS_SRC_PLLFIX, 156, 0u},
{R_DEV_CKS_ISM, R_DEV_CKS_SRC_CLKJIT, 0, 0u},
/* delimiter - do not remove */
{R_DEV_CKS_LAST, R_DEV_CKS_SRC_MOSC, 2, 0u},
};
void Clock_Pre_Init(void)
{
/* use the config, call Clock Gen Init */
R_DEV_ClkGenInit((r_dev_ClkGenConfig_t *)(&g_stClockGenCfg), g_stClkSelectionCfg);
/* use the config, store settings (needs to be repeated after low init */
R_DEV_ClkGenInitStore((r_dev_ClkGenConfig_t *)(&g_stClockGenCfg));
}
void Clock_Init(void)
{
/* use the config, store settings */
R_DEV_ClkGenInitStore((r_dev_ClkGenConfig_t *)(&g_stClockGenCfg));
}
/*Clock monitor initialization*/
static void Clock_Monitor_A_Init(void)
{
/*only open monitor2 ，Monitor main clock*/
CLMA2CMPH = 652U; /*+-10%*/
CLMA2CMPL = 435U; /*+-10%*/
CLOCK_PROTECTED_WRITE(CLMA2PCMD, CLMA2PS, CLMA2CTL0, 0x01U);
}
/*Stop all of the modules before Call the following function,except RTC*/
/*falling edge detection*/
void Clock_Enter_Sleep_Mode(void)
{
/*Stop modules*/
/*port buffer into hold state*/
/*Disable interrupt*/
/*Clear the interrupt flag*/
/*config interrupt , mask or unmask*/
/*Clear wake-up flag*/
/*Config wake-up factors*/
/*You can choose more than one PIN*/
/*(Except in D1M1A and D1M1-V2) ,Change CPU clock to EMCLK*/
CLOCK_PROTECTED_WRITE(SYSPROTCMD1, SYSPROTS1, SYSCKSC_ICPUCLKS_CTL, 0x01U); /*select EMCLK*/
/*Config clock domains . It's already set up in the initialization function */
/*MainOsc continues operation in DEEPSTOP mode*/
SYSMOSCSTPM = 0x03U;
/*High Speed IntOsc stops operation in DEEPSTOP mode.*/
//SYSROSCSTPM = 0x02U;
R_DEV_SetGenStopMask(R_DEV_HS_RING, 0U);
/*Clock domain C_AWO_AWOT is stopped in DEEPSTOP mode*/
SYSCKSC_AAWOTD_STPM = 0x02U;
/*Clock domain C_AWO_RTCA is not stopped in DEEPSTOP mode*/
SYSCKSC_ARTCAD_STPM = 0X03U;
/*Clock domain C_AWO_FOUT is stopped in DEEPSTOP mode*/
SYSCKSC_AFOUTS_STPM = 0X02U;
/*Stop all active PLLs*/
//CLOCK_PROTECTED_WRITE(SYSPROTCMD1, SYSPROTS1, SYSPLL0E, 0x02U); /*Stop the PLL0*/
//CLOCK_PROTECTED_WRITE(SYSPROTCMD1, SYSPROTS1, SYSPLL1E, 0x02U); /*Stop the PLL1*/
R_DEV_ClkGenStop(R_DEV_PLL0);
R_DEV_ClkGenStop(R_DEV_PLL1);
/*Clear the RESF register*/
/*start DEEPSTOP mode*/
/*wait for the transition to the DEEPSTOP mode by the unconditional loop*/
}
Clock_Startup_Mode_en_t Clock_Get_Startup_Mode(void)
{
Clock_Startup_Mode_en_t enClockMode;
uint32_t u32ResetRESFValue = 0U;
uint32_t u32ResetRESFRValue = 0U;
/* Read reset factor */
u32ResetRESFValue = SYSRESF;
u32ResetRESFRValue = SYSRESFR;
/* Clear reset factor */
SYSRESFC = 0xC70FU;
SYSRESFCR = 0xC70FU;
if (u32ResetRESFValue & 0x00000200U) /*Power-up reset PURES: POC0RES,DBRES*/
{
enClockMode = CLOCK_STARTUP_PWR_ON;
}
else if (u32ResetRESFValue & 0x00004400U) /* DEEPSTOP reset ISORES ,Error Control Module */
{
enClockMode = CLOCK_STARTUP_WAKE_UP;
}
else /*System reset SYSRES:WDTA1,WDTA0 ,Software and so on */
{
enClockMode = CLOCK_STARTUP_SYSTEM_RESET;
}
return enClockMode;
}
static uint32_t wbytest = 0 ;
void Sys_Enter_Sleep_Mode(void)
{
WDT_Clear();
CLOCK_PROTECTED_WRITE(SYSPROTCMD0, SYSPROTS0, SYSCKSC_AWDTA0D_CTL, 0x06U); /* 看门狗时钟2048分频*/
__DI();
SYSWUFC0 = 0x7FFFFU;
/*---------------------------------------------*/
//GPIO_Wakeup_PIN_Set(GPIO_WAKEUP_PIN_P0_5, GPIO_WAKEUP_FALLING_EDGE);
GPIO_Wakeup_PIN_Set(GPIO_WAKEUP_PIN_P0_0, GPIO_WAKEUP_RISING_EDGE);
/*----------------------------------------------*/
SYSWUFMSK0 &= 0x7FFFEU;
Clock_Enter_Sleep_Mode();
SYSRESFC = 0xC70FU;
CLOCK_PROTECTED_WRITE(SYSPROTCMD0, SYSPROTS0, SYSSTBC0PSC, 0x02U);
for (;;)
{
wbytest ++ ;
}
}
#include "r_typedefs.h"
#include "dr7f701441.dvf.h"
#include "r_dev_clk_types.h"
#include "r_dev_api.h"
#include "Clock.h"
#include "GPIO.h"
#include "Watchdog.h"
#include "TYW_FLASH.h"
#include "RTC.h"
#include "rh850_macros.h"
extern uint32_t TestBackupRam;
#define CLOCK_PROTECTED_WRITE(preg, pstatus, reg, value) \
do \
{ \
(preg) = 0xA5U; \
(reg) = (value); \
(reg) = ~(value); \
(reg) = (value); \
} while ((pstatus) == 1U)
static const r_dev_ClkGenConfig_t g_stClockGenCfg =
{
/*mainosc*/
{
/* FrequencyHz */ R_DEV_MOSC_FRQ_HZ,
/* StabiTimeNs */ 400000UL,
/* Gain */ 3U,
/* Running */ 1U,
/* StpReqMsk */ 1U,
},
/*subosc*/
{
/* FrequencyHz */ 32768UL,
/* Running */ 0U,
/* StpReqMsk */ 0U,
},
/* PLL */
{
/*PLL0*/
{
/* Mode */ R_DEV_PLL_SSCG,
/* DithMode */ R_DEV_PLL_DITH_DOWN,
/* DithRange */ 3U,
/* ModFreq */ 50UL,
/* FrequencyHz */ 480UL * 1000UL * 1000UL,
/* StabiTimeNs */ 40000UL,
/* StpReqMsk */ 0U,
},
/*PLL1*/
{
/* Mode */ R_DEV_PLL_ON,
/* DithMode */ R_DEV_PLL_DITH_FIXED,
/* DithRange */ 0U,
/* ModFreq */ 0UL,
/* FrequencyHz */ 480UL * 1000UL * 1000UL,
/* StabiTimeNs */ 40000UL,
/* StpReqMsk */ 0U,
},
/*PLL2*/
{
/* Mode */ R_DEV_PLL_OFF,
/* DithMode */ R_DEV_PLL_DITH_FIXED,
/* DithRange */ 0U,
/* ModFreq */ 0UL,
/* FrequencyHz */ 0UL,
/* StabiTimeNs */ 0UL,
/* StpReqMsk */ 0U,
},
},
/* ROSC */
/* RoscStpReqMsk */ 1U,
/* BusEnable */
{
/* R_DEV_CLK_PLL0 */ 1U,
/* R_DEV_CLK_PLL1 */ 1U,
/* R_DEV_CLK_PLL2 */ 0U,
/* R_DEV_CLK_PLL0PIX */ 1U,
/* R_DEV_CLK_SDRB */ 1U,
/* R_DEV_CLK_ETNBP */ 1U,
/* R_DEV_CLK_MLBP */ 1U,
/* R_DEV_CLK_RSCANP */ 1U,
/* R_DEV_CLK_XCC */ 1U,
/* R_DEV_CLK_ETNBXCC */ 1U,
/* R_DEV_CLK_MLBXCC */ 1U,
},
};
static const r_dev_ClkSelConfig_t g_stClkSelectionCfg[] =
/* Cks SrcId Div StpReqMsk */
{
/* {R_DEV_CKS_RSCAN, R_DEV_CKS_SRC_PLLFIX, } */
{R_DEV_CKS_RSCANXIN, R_DEV_CKS_SRC_MOSC, 1, 0u},
{R_DEV_CKS_WDT0, R_DEV_CKS_SRC_LRNG, 256, 0u},
{R_DEV_CKS_RTC, R_DEV_CKS_SRC_MOSC, 2, 0u},
{R_DEV_CKS_OSTM, R_DEV_CKS_SRC_MOSC, 2, 0u},
{R_DEV_CKS_CLKJIT, R_DEV_CKS_SRC_DIV, 6, 0u},
{R_DEV_CKS_PLLFIX, R_DEV_CKS_SRC_PLL1, 1, 0u},
{R_DEV_CKS_CLKFIX, R_DEV_CKS_SRC_DIV, 6, 0u},
{R_DEV_CKS_CPU, R_DEV_CKS_SRC_PLL0, 2, 0u},
{R_DEV_CKS_SFMA, R_DEV_CKS_SRC_PLL0, 3, 0u},
{R_DEV_CKS_SSIF, R_DEV_CKS_SRC_PLLFIX, 156, 0u},
/* delimiter - do not remove */
{R_DEV_CKS_LAST, R_DEV_CKS_SRC_MOSC, 2, 0u},
};
void Clock_Pre_Init(void)
{
/* use the config, call Clock Gen Init */
R_DEV_ClkGenInit((r_dev_ClkGenConfig_t *)(&g_stClockGenCfg), g_stClkSelectionCfg);
/* use the config, store settings (needs to be repeated after low init */
R_DEV_ClkGenInitStore((r_dev_ClkGenConfig_t *)(&g_stClockGenCfg));
}
void Clock_Init(void)
{
/* use the config, store settings */
R_DEV_ClkGenInitStore((r_dev_ClkGenConfig_t *)(&g_stClockGenCfg));
}
/*Clock monitor initialization*/
static void Clock_Monitor_A_Init(void)
{
/*only open monitor2 ，Monitor main clock*/
CLMA2CMPH = 652U; /*+-10%*/
CLMA2CMPL = 435U; /*+-10%*/
CLOCK_PROTECTED_WRITE(CLMA2PCMD, CLMA2PS, CLMA2CTL0, 0x01U);
}
/*Stop all of the modules before Call the following function,except RTC*/
/*falling edge detection*/
void Clock_Enter_Sleep_Mode(void)
{
/*Stop modules*/
/*port buffer into hold state*/
/*Disable interrupt*/
/*Clear the interrupt flag*/
/*config interrupt , mask or unmask*/
/*Clear wake-up flag*/
/*Config wake-up factors*/
/*You can choose more than one PIN*/
/*(Except in D1M1A and D1M1-V2) ,Change CPU clock to EMCLK*/
CLOCK_PROTECTED_WRITE(SYSPROTCMD1, SYSPROTS1, SYSCKSC_ICPUCLKS_CTL, 0x01U); /*select EMCLK*/
/*Config clock domains . It's already set up in the initialization function */
/*MainOsc continues operation in DEEPSTOP mode*/
SYSMOSCSTPM = 0x03U;
/*High Speed IntOsc stops operation in DEEPSTOP mode.*/
// SYSROSCSTPM = 0x02U;
R_DEV_SetGenStopMask(R_DEV_HS_RING, 0U);
/*Clock domain C_AWO_AWOT is stopped in DEEPSTOP mode*/
SYSCKSC_AAWOTD_STPM = 0x02U;
/*Clock domain C_AWO_RTCA is not stopped in DEEPSTOP mode*/
SYSCKSC_ARTCAD_STPM = 0X03U;
/*Clock domain C_AWO_FOUT is stopped in DEEPSTOP mode*/
SYSCKSC_AFOUTS_STPM = 0X02U;
/*Stop all active PLLs*/
// CLOCK_PROTECTED_WRITE(SYSPROTCMD1, SYSPROTS1, SYSPLL0E, 0x02U); /*Stop the PLL0*/
// CLOCK_PROTECTED_WRITE(SYSPROTCMD1, SYSPROTS1, SYSPLL1E, 0x02U); /*Stop the PLL1*/
R_DEV_ClkGenStop(R_DEV_PLL0);
R_DEV_ClkGenStop(R_DEV_PLL1);
/*Clear the RESF register*/
/*start DEEPSTOP mode*/
/*wait for the transition to the DEEPSTOP mode by the unconditional loop*/
}
#pragma ghs section bss = ".absinitarea"
uint32_t u32ResetFlag;
uint32_t u32ResetSource;
#pragma ghs section bss = default
Clock_Startup_Mode_en_t Clock_Get_Startup_Mode(void)
{
Clock_Startup_Mode_en_t enClockMode;
uint32_t u32ResetRESFValue = 0U;
uint32_t u32ResetRESFRValue = 0U;
/* Read reset factor */
u32ResetRESFValue = SYSRESF;
u32ResetRESFRValue = SYSRESFR;
u32ResetSource = SYSRESF;
/* Clear reset factor */
SYSRESFC = 0xC70FU;
SYSRESFCR = 0xC70FU;
if (u32ResetRESFValue & 0x0000C30FU)
{
enClockMode = CLOCK_STARTUP_PWR_ON;
}
else
{
enClockMode = CLOCK_STARTUP_WAKE_UP;
}
return enClockMode;
}
void Sys_Enter_Sleep_Mode(void)
{
WDT_Clear();
CLOCK_PROTECTED_WRITE(SYSPROTCMD0, SYSPROTS0, SYSCKSC_AWDTA0D_CTL, 0x06U); /* 看门狗时钟2048分频*/
GPIO_Init(GPIO_SLEEP_MODE);
__DI();
SYSWUFC0 = 0x7FFFFU;
/*---------------------------------------------*/
GPIO_Wakeup_PIN_Set(GPIO_WAKEUP_PIN_P0_5, GPIO_WAKEUP_FALLING_EDGE);
GPIO_Wakeup_PIN_Set(GPIO_WAKEUP_PIN_P0_0, GPIO_WAKEUP_RISING_EDGE);
/*----------------------------------------------*/
SYSWUFMSK0 &= 0x7FFFEU;
Clock_Enter_Sleep_Mode();
SYSRESFC = 0xC70FU;
CLOCK_PROTECTED_WRITE(SYSPROTCMD0, SYSPROTS0, SYSSTBC0PSC, 0x02U);
RTC_Backup_Time();
TestBackupRam = 0xaabbccddu;
hardware_reset();
}
source/Driver/Clock/Clock.h
View file @ f3345a2c
#ifndef CLOCK_H__
#define CLOCK_H__
/*Oscillator*/
#define CLOCK_MAIN_OSC_FREQ_HZ (8000000UL)
#define CLOCK_SUB_OSC_FREQ_HZ (0UL) /*32768U*/
#define CLOCK_FAST_CR_OSC_FREQ_HZ (8000000UL)
#define CLOCK_SLOW_CR_OSC_FREQ_HZ (240000UL)
#define CLOCK_EMCLK_FREQ_HZ (CLOCK_FAST_CR_OSC_FREQ_HZ)
/* PLL */
#define CLOCK_PLL0_FREQ_HZ (480000000UL)
#define CLOCK_PLL1_FREQ_HZ (480000000UL)
#define CLOCK_PLLFIX_FREQ_HZ (CLOCK_PLL1_FREQ_HZ)
#define CLOCK_JIT_FREQ_HZ (80000000UL)
#define CLOCK_FIX_FREQ_HZ (80000000UL)
#define CLOCK_SDRB_FREQ_HZ (240000000UL)
#define CLOCK_CPU_FREQ_HZ (240000000UL)
#define CLOCK_XC_FREQ_HZ (120000000UL)
#define CLOCK_PCLK_FREQ_HZ (CLOCK_XC_FREQ_HZ / 2)
#define CLOCK_ETNBP_FREQ_HZ (60000000UL) /*Enable or Disable*/
#define CLOCK_ETNBXC_FREQ_HZ (120000000UL) /*Enable or Disable*/
#define CLOCK_RSCANP_FREQ_HZ (80000000UL) /*Enable or Disable*/
#define CLOCK_AWOT_FREQ_HZ (8000000UL)
#define CLOCK_WDTA0_FREQ_HZ (240000UL)
#define CLOCK_RTCA_FREQ_HZ (4000000UL)
#define CLOCK_FOUT_FREQ_HZ (20000000UL)
#define CLOCK_SFMA_FREQ_HZ (240000000UL)
#define CLOCK_RSCAN_FREQ_HZ (40000000UL)
#define CLOCK_RSCANXIN_FREQ_HZ (16000000UL) /*MAIN_OSC or Disable*/
#define CLOCK_SSIF_FREQ_HZ (50000000UL)
#define CLOCK_TAUB01_FREQ_HZ (80000000UL)
#define CLOCK_TAUB2_FREQ_HZ (80000000UL)
#define CLOCK_TAUJ_FREQ_HZ (80000000UL)
#define CLOCK_OSTM_FREQ_HZ (80000000UL)
/*#define CLOCK_LCBI_FREQ_HZ (CLOCK_JIT_FREQ_HZ)*/
#define CLOCK_ADCE_FREQ_HZ (40000000UL)
#define CLOCK_ISM_FREQ_HZ (80000000UL)
#define CLOCK_RLIN_FREQ_HZ (48000000UL)
/* Registers */
#define CLOCK_CFG_CLKJIT_DIVIDER (0x0001010FUL)
#define CLOCK_CFG_CLKJIT_SOURCE (0x00210100UL)
#define CLOCK_CFG_CLKJIT_ACTIVE (0x00210100UL)
typedef enum
{
CLOCK_STARTUP_PWR_ON = 0,
CLOCK_STARTUP_WAKE_UP,
CLOCK_STARTUP_SYSTEM_RESET,
} Clock_Startup_Mode_en_t;
extern void Clock_Pre_Init(void);
extern void Clock_Init(void);
extern void Clock_Enter_Sleep_Mode(void);
extern Clock_Startup_Mode_en_t Clock_Get_Startup_Mode(void);
extern void Sys_Enter_Sleep_Mode(void);
#endif
#ifndef CLOCK_H__
#define CLOCK_H__
/*Oscillator*/
#define CLOCK_MAIN_OSC_FREQ_HZ (8000000UL)
#define CLOCK_SUB_OSC_FREQ_HZ (0UL) /*32768U*/
#define CLOCK_FAST_CR_OSC_FREQ_HZ (8000000UL)
#define CLOCK_SLOW_CR_OSC_FREQ_HZ (240000UL)
#define CLOCK_EMCLK_FREQ_HZ (CLOCK_FAST_CR_OSC_FREQ_HZ)
/* PLL */
#define CLOCK_PLL0_FREQ_HZ (480000000UL)
#define CLOCK_PLL1_FREQ_HZ (480000000UL)
#define CLOCK_PLLFIX_FREQ_HZ (CLOCK_PLL1_FREQ_HZ)
#define CLOCK_JIT_FREQ_HZ (80000000UL)
#define CLOCK_FIX_FREQ_HZ (80000000UL)
#define CLOCK_SDRB_FREQ_HZ (240000000UL)
#define CLOCK_CPU_FREQ_HZ (240000000UL)
#define CLOCK_XC_FREQ_HZ (120000000UL)
#define CLOCK_PCLK_FREQ_HZ (CLOCK_XC_FREQ_HZ / 2)
#define CLOCK_ETNBP_FREQ_HZ (60000000UL) /*Enable or Disable*/
#define CLOCK_ETNBXC_FREQ_HZ (120000000UL) /*Enable or Disable*/
#define CLOCK_RSCANP_FREQ_HZ (80000000UL) /*Enable or Disable*/
#define CLOCK_AWOT_FREQ_HZ (8000000UL)
#define CLOCK_WDTA0_FREQ_HZ (240000UL)
#define CLOCK_RTCA_FREQ_HZ (4000000UL)
#define CLOCK_FOUT_FREQ_HZ (20000000UL)
#define CLOCK_SFMA_FREQ_HZ (240000000UL)
#define CLOCK_RSCAN_FREQ_HZ (40000000UL)
#define CLOCK_RSCANXIN_FREQ_HZ (16000000UL) /*MAIN_OSC or Disable*/
#define CLOCK_SSIF_FREQ_HZ (50000000UL)
#define CLOCK_TAUB01_FREQ_HZ (80000000UL)
#define CLOCK_TAUB2_FREQ_HZ (80000000UL)
#define CLOCK_TAUJ_FREQ_HZ (80000000UL)
#define CLOCK_OSTM_FREQ_HZ (80000000UL)
/*#define CLOCK_LCBI_FREQ_HZ (CLOCK_JIT_FREQ_HZ)*/
#define CLOCK_ADCE_FREQ_HZ (40000000UL)
#define CLOCK_ISM_FREQ_HZ (80000000UL)
#define CLOCK_RLIN_FREQ_HZ (48000000UL)
/* Registers */
#define CLOCK_CFG_CLKJIT_DIVIDER (0x0001010FUL)
#define CLOCK_CFG_CLKJIT_SOURCE (0x00210100UL)
#define CLOCK_CFG_CLKJIT_ACTIVE (0x00210100UL)
typedef enum
{
CLOCK_STARTUP_PWR_ON = 0,
CLOCK_STARTUP_WAKE_UP,
CLOCK_STARTUP_SYSTEM_RESET,
} Clock_Startup_Mode_en_t;
extern void Clock_Pre_Init(void);
extern void Clock_Init(void);
extern void Clock_Enter_Sleep_Mode(void);
extern Clock_Startup_Mode_en_t Clock_Get_Startup_Mode(void);
extern void Sys_Enter_Sleep_Mode(void);
#endif
source/Driver/Clock/RTC.c
View file @ f3345a2c
#include "r_typedefs.h"
#include "dr7f701441.dvf.h"
#include "RTC.h"
volatile uint8_t g_RTCLeapYear; /*1:LeapYear , 0:Not a leap year*/
volatile RTC_Information_st_t g_stRTCInformation;
static uint8_t Cal_RTC_Week(uint16_t Year, uint8_t Month, uint8_t Day);
/* BCD Convert decimalism*/
/*The valid range of parameters is not judged*/
static uint8_t RTC_BCD_To_Dec(uint8_t u8RTCBCD)
{
uint8_t u8RTCData = ((u8RTCBCD >> 4U) * 10U) + (u8RTCBCD & 0X0FU);
return u8RTCData;
}
/* decimalism Convert BCD */
static uint8_t RTC_Dec_To_BCD(uint8_t u8RTCDec)
{
uint8_t u8RTCData = (((u8RTCDec / 10U) % 10U) << 4U) + (u8RTCDec % 10U);
return u8RTCData;
}
/**************************************************************************/ /**
* \brief Determine if a year is leap year
* \param Year: the year to be determined
* \retval \arg 0: Not leap year
* \arg 1: Leap year
******************************************************************************/
static uint8_t RTC_Determine_Leap_Year(uint16_t Year)
{
uint16_t u16RTCLeapYear = Year;
/*u16RTCLeapYear = ((Year >> 4) & 0x0F) * 10 + (Year & 0x0F);*/
if (u16RTCLeapYear & 0x0003U)
{
u16RTCLeapYear = 0U;
}
else
{
u16RTCLeapYear = 1U;
}
return (uint8_t)u16RTCLeapYear;
}
static void RTC_Stop(void)
{
/*Stop sub-counter */
RTCA0CE = 0U;
/*Wait sub-counter stop*/
while (RTCA0CEST != 0)
{
;
}
}
void RTC_Pre_Init(void)
{
RTC_Stop(); /* Stop RTCA*/
#if (RTC_MODE_SELECT == RTC_MODE_MAIN)
RTCA0SLSB = 1U; /*Frequency selection mode*/
RTCA0SCMP = 4000000U - 1U; /*4M*/
#else
RTCA0SLSB = 0U; /*32.768 kHz mode*/
RTCA0SUBU = 0U; /*Reserved Later modified,Error Correction*/
#endif
RTCA0AMPM = 1U; /*fix 24Hour Format*/
/*Write start values*/
RTCA0YEAR = RTC_Dec_To_BCD(RTC_DEFAULT_YEAR);
RTCA0MONTH = RTC_Dec_To_BCD(RTC_DEFAULT_MONTH);
RTCA0DAY = RTC_Dec_To_BCD(RTC_DEFAULT_DATE);
RTCA0HOUR = RTC_Dec_To_BCD(RTC_DEFAULT_HOUR);
RTCA0MIN = RTC_Dec_To_BCD(RTC_DEFAULT_MINUTE);
RTCA0SEC = RTC_Dec_To_BCD(RTC_DEFAULT_SECOND);
/*Starts sub-counter*/
RTCA0CE = 1U;
/*Wait sub-counter enable*/
while (RTCA0CEST != 1U)
{
;
}
}
void RTC_Set_Time(RTC_Information_st_t *pstRTCTime)
{
while (RTCA0WST != 0U) /*Check that all clock counters are running.*/
{
;
}
RTCA0WAIT = 1U; /*Stop all clock counters*/
while (RTCA0WST != 1U) /*Wait all clock counters stop*/
{
;
}
/*Write start values*/
RTCA0YEAR = RTC_Dec_To_BCD(pstRTCTime->u8RTCYear);
RTCA0MONTH = RTC_Dec_To_BCD(pstRTCTime->u8RTCMonth);
RTCA0DAY = RTC_Dec_To_BCD(pstRTCTime->u8RTCDayOfMonth);
RTCA0HOUR = RTC_Dec_To_BCD(pstRTCTime->u8RTCHour);
RTCA0MIN = RTC_Dec_To_BCD(pstRTCTime->u8RTCMinute);
RTCA0SEC = RTC_Dec_To_BCD(pstRTCTime->u8RTCSecond);
/*Start all clock counters*/
RTCA0WAIT = 0U;
while (RTCA0WST != 0U) /*Check that all clock counters are running.*/
{
;
}
}
/**************************************************************************/ /**
* \brief Rreal time clock timing control
* \attention Call this function every 100 ms.
* \retval None
******************************************************************************/
void RTC_Timing_Service(void)
{
uint8_t Week = 0 ;
while (RTCA0WST != 0U) /*Check that all clock counters are running.*/
{
;
}
RTCA0WAIT = 1U; /*Stop all clock counters*/
while (RTCA0WST != 1U) /*Wait all clock counters stop*/
{
;
}
/*Read data*/
g_stRTCInformation.u8RTCYear = RTC_BCD_To_Dec(RTCA0YEAR);
g_stRTCInformation.u8RTCMonth = RTC_BCD_To_Dec(RTCA0MONTH);
g_stRTCInformation.u8RTCDayOfMonth = RTC_BCD_To_Dec(RTCA0DAY);
g_stRTCInformation.u8RTCHour = RTC_BCD_To_Dec(RTCA0HOUR);
g_stRTCInformation.u8RTCMinute = RTC_BCD_To_Dec(RTCA0MIN);
g_stRTCInformation.u8RTCSecond = RTC_BCD_To_Dec(RTCA0SEC);
Week = Cal_RTC_Week(g_stRTCInformation.u8RTCYear, g_stRTCInformation.u8RTCMonth, g_stRTCInformation.u8RTCDayOfMonth);
g_stRTCInformation.u8RTCWeek = Week ;
g_RTCLeapYear = RTC_Determine_Leap_Year(g_stRTCInformation.u8RTCYear);
/*Start all clock counters*/
RTCA0WAIT = 0U;
while (RTCA0WST != 0U) /*Check that all clock counters are running.*/
{
;
}
}
void RTC_Init(void)
{
RTC_Timing_Service();
}
/*计算 星期几*/
static uint8_t Cal_RTC_Week(uint16_t Year, uint8_t Month, uint8_t Day)
{
if (Month < 3)
{
Month += 12;
Year--;
}
uint8_t tmp_0 = (uint8_t)(Year % 100);
uint8_t tmp_1 = (uint8_t)(Year / 100);
uint8_t week = (uint8_t)((tmp_0 + (tmp_0 >> 2) + (tmp_1 >> 2) + 13 * (Month + 1) / 5 + Day - 1 - (tmp_1 << 1)) % 7);
return week;
}
#include "r_typedefs.h"
#include "dr7f701441.dvf.h"
#include "RTC.h"
#include <string.h>
RTC_Information_st_t g_stRTCInformation;
#define RTC_TIME_OUT_COUNT 500U
static uint8_t Cal_RTC_Week(uint16_t Year, uint8_t Month, uint8_t Day);
/* BCD Convert decimalism*/
/*The valid range of parameters is not judged*/
static uint8_t RTC_BCD_To_Dec(uint8_t u8RTCBCD)
{
uint8_t u8RTCData = ((u8RTCBCD >> 4U) * 10U) + (u8RTCBCD & 0X0FU);
return u8RTCData;
}
/* decimalism Convert BCD */
static uint8_t RTC_Dec_To_BCD(uint8_t u8RTCDec)
{
uint8_t u8RTCData = (((u8RTCDec / 10U) % 10U) << 4U) + (u8RTCDec % 10U);
return u8RTCData;
}
static void RTC_Stop(void)
{
uint16_t u16RTCCount = 0U;
/*Stop sub-counter */
RTCA0CE = 0U;
/*Wait sub-counter stop*/
while ((RTCA0CEST != 0) && (u16RTCCount < RTC_TIME_OUT_COUNT))
{
u16RTCCount++;
}
}
void RTC_Pre_Init(void)
{
uint16_t u16RTCCount = 0U;
RTC_Stop(); /* Stop RTCA*/
#if (RTC_MODE_SELECT == RTC_MODE_MAIN)
RTCA0SLSB = 1U; /*Frequency selection mode*/
RTCA0SCMP = 4000000U - 1U; /*4M*/
#else
RTCA0SLSB = 0U; /*32.768 kHz mode*/
RTCA0SUBU = 0U; /*Reserved Later modified,Error Correction*/
#endif
RTCA0AMPM = 1U; /*fix 24Hour Format*/
/*Write start values*/
RTCA0YEAR = RTC_Dec_To_BCD(RTC_DEFAULT_YEAR);
RTCA0MONTH = RTC_Dec_To_BCD(RTC_DEFAULT_MONTH);
RTCA0DAY = RTC_Dec_To_BCD(RTC_DEFAULT_DATE);
RTCA0HOUR = RTC_Dec_To_BCD(RTC_DEFAULT_HOUR);
RTCA0MIN = RTC_Dec_To_BCD(RTC_DEFAULT_MINUTE);
RTCA0SEC = RTC_Dec_To_BCD(RTC_DEFAULT_SECOND);
/*Starts sub-counter*/
RTCA0CE = 1U;
u16RTCCount = 0U;
/*Wait sub-counter enable*/
while ((RTCA0CEST != 1U) && (u16RTCCount < RTC_TIME_OUT_COUNT))
{
u16RTCCount++;
}
}
void RTC_Set_Time(uint8_t year, uint8_t month, uint16_t day, uint8_t hour, uint8_t minute, uint8_t second)
{
uint16_t u16RTCCount = 0U;
while ((RTCA0WST != 0U) && (u16RTCCount < RTC_TIME_OUT_COUNT)) /*Check that all clock counters are running.*/
{
u16RTCCount++;
}
RTCA0WAIT = 1U; /*Stop all clock counters*/
u16RTCCount = 0U;
while ((RTCA0WST != 1U) && (u16RTCCount < RTC_TIME_OUT_COUNT)) /*Wait all clock counters stop*/
{
u16RTCCount++;
}
/*Write start values*/
RTCA0YEAR = RTC_Dec_To_BCD(year);
RTCA0MONTH = RTC_Dec_To_BCD(month);
RTCA0DAY = RTC_Dec_To_BCD(day);
RTCA0HOUR = RTC_Dec_To_BCD(hour);
RTCA0MIN = RTC_Dec_To_BCD(minute);
RTCA0SEC = RTC_Dec_To_BCD(second);
/*Start all clock counters*/
RTCA0WAIT = 0U;
u16RTCCount = 0U;
while ((RTCA0WST != 0U) && (u16RTCCount < RTC_TIME_OUT_COUNT)) /*Check that all clock counters are running.*/
{
u16RTCCount++;
}
}
void RTC_Get_Time(void)
{
uint16_t u16RTCCount = 0U;
uint8_t Week = 0 ;
while ((RTCA0WST != 0U) && (u16RTCCount < RTC_TIME_OUT_COUNT)) /*Check that all clock counters are running.*/
{
u16RTCCount++;
}
RTCA0WAIT = 1U; /*Stop all clock counters*/
u16RTCCount = 0U;
while ((RTCA0WST != 1U) && (u16RTCCount < RTC_TIME_OUT_COUNT)) /*Wait all clock counters stop*/
{
u16RTCCount++;
}
/*Read data*/
g_stRTCInformation.u8RTCYear = RTC_BCD_To_Dec(RTCA0YEAR);
g_stRTCInformation.u8RTCMonth = RTC_BCD_To_Dec(RTCA0MONTH);
g_stRTCInformation.u8RTCDayOfMonth = RTC_BCD_To_Dec(RTCA0DAY);
g_stRTCInformation.u8RTCHour = RTC_BCD_To_Dec(RTCA0HOUR);
g_stRTCInformation.u8RTCMinute = RTC_BCD_To_Dec(RTCA0MIN);
g_stRTCInformation.u8RTCSecond = RTC_BCD_To_Dec(RTCA0SEC);
Week = Cal_RTC_Week(g_stRTCInformation.u8RTCYear, g_stRTCInformation.u8RTCMonth, g_stRTCInformation.u8RTCDayOfMonth);
g_stRTCInformation.u8RTCWeek = Week ;
/*Start all clock counters*/
RTCA0WAIT = 0U;
u16RTCCount = 0U;
while ((RTCA0WST != 0U) && (u16RTCCount < RTC_TIME_OUT_COUNT)) /*Check that all clock counters are running.*/
{
u16RTCCount++;
}
}
#pragma ghs section bss=".NonInitArea"
RTC_Information_st_t RtcBackup;
#pragma ghs section bss=default
void RTC_Backup_Time(void)
{
RTC_Get_Time();
memcpy((uint8_t*)&RtcBackup, (uint8_t*)&g_stRTCInformation, sizeof (RtcBackup));
}
void Rtc_Restore_Time(void)
{
uint16_t u16RTCCount = 0U;
RTC_Stop(); /* Stop RTCA*/
#if (RTC_MODE_SELECT == RTC_MODE_MAIN)
RTCA0SLSB = 1U; /*Frequency selection mode*/
RTCA0SCMP = 4000000U - 1U; /*4M*/
#else
RTCA0SLSB = 0U; /*32.768 kHz mode*/
RTCA0SUBU = 0U; /*Reserved Later modified,Error Correction*/
#endif
RTCA0AMPM = 1U; /*fix 24Hour Format*/
/*Write start values*/
RTCA0YEAR = RTC_Dec_To_BCD(RtcBackup.u8RTCYear);
RTCA0MONTH = RTC_Dec_To_BCD(RtcBackup.u8RTCMonth);
RTCA0DAY = RTC_Dec_To_BCD(RtcBackup.u8RTCDayOfMonth);
RTCA0HOUR = RTC_Dec_To_BCD(RtcBackup.u8RTCHour);
RTCA0MIN = RTC_Dec_To_BCD(RtcBackup.u8RTCMinute);
RTCA0SEC = RTC_Dec_To_BCD(RtcBackup.u8RTCSecond);
/*Starts sub-counter*/
RTCA0CE = 1U;
u16RTCCount = 0U;
/*Wait sub-counter enable*/
while ((RTCA0CEST != 1U) && (u16RTCCount < RTC_TIME_OUT_COUNT))
{
u16RTCCount++;
}
}
/* ڼ*/
static uint8_t Cal_RTC_Week(uint16_t Year, uint8_t Month, uint8_t Day)
{
if (Month < 3)
{
Month += 12;
Year--;
}
uint8_t tmp_0 = (uint8_t)(Year % 100);
uint8_t tmp_1 = (uint8_t)(Year / 100);
uint8_t week = (uint8_t)((tmp_0 + (tmp_0 >> 2) + (tmp_1 >> 2) + 13 * (Month + 1) / 5 + Day - 1 - (tmp_1 << 1)) % 7);
return week;
}
source/Driver/Clock/RTC.h
View file @ f3345a2c
#ifndef RTC_H__
#define RTC_H__
#include "r_typedefs.h"
#define RTC_MODE_MAIN 0U
#define RTC_MODE_SUB 1U
#define RTC_MODE_SELECT RTC_MODE_MAIN
/* RTC default time setting */
#ifndef RTC_DEFAULT_TIME
#define RTC_DEFAULT_TIME 1U
#define RTC_DEFAULT_YEAR 21U
#define RTC_DEFAULT_MONTH 1U
#define RTC_DEFAULT_DATE 1U
#define RTC_DEFAULT_HOUR 0U
#define RTC_DEFAULT_MINUTE 0U
#define RTC_DEFAULT_SECOND 0U
#endif
typedef struct
{
uint8_t u8RTCYear; /*00~~99 in Dec*/
uint8_t u8RTCMonth; /*01~~12 in Dec*/
uint8_t u8RTCDayOfMonth; /*01~~31 in Dec*/
uint8_t u8RTCHour; /*fix 24Hour Format 00~~23 in Dec*/
uint8_t u8RTCMinute; /*0~~59 in Dec*/
uint8_t u8RTCSecond; /*0~~59 in Dec*/
uint8_t u8RTCWeek ; /*1~7 in Dec*/
} RTC_Information_st_t;
extern volatile uint8_t g_RTCLeapYear; /*1:LeapYear , 0:Not a leap year*/
extern volatile RTC_Information_st_t g_stRTCInformation;
/* RTC exported time register */
#define RTC_YEAR g_stRTCInformation.u8RTCYear
#define RTC_MONTH g_stRTCInformation.u8RTCMonth
#define RTC_DATE g_stRTCInformation.u8RTCDayOfMonth
#define RTC_HOUR g_stRTCInformation.u8RTCHour
#define RTC_MINUTE g_stRTCInformation.u8RTCMinute
#define RTC_SECOND g_stRTCInformation.u8RTCSecond
#define RTC_WEEK g_stRTCInformation.u8RTCWeek
#define RTC_LEAP_YEAR g_RTCLeapYear
extern void RTC_Pre_Init(void);
extern void RTC_Init(void);
extern void RTC_Set_Time(RTC_Information_st_t *pstRTCTime);
extern void RTC_Timing_Service(void);
#endif
#ifndef RTC_H__
#define RTC_H__
#include "r_typedefs.h"
#define RTC_MODE_MAIN 0U
#define RTC_MODE_SUB 1U
#define RTC_MODE_SELECT RTC_MODE_MAIN
//#ifndef RTC_DEFAULT_TIME
#define RTC_DEFAULT_TIME 1U
#define RTC_DEFAULT_YEAR 21U
#define RTC_DEFAULT_MONTH 1U
#define RTC_DEFAULT_DATE 1U
#define RTC_DEFAULT_HOUR 0U
#define RTC_DEFAULT_MINUTE 0U
#define RTC_DEFAULT_SECOND 0U
//#endif
typedef struct
{
uint8_t u8RTCYear; /*00~~99 in Dec*/
uint8_t u8RTCMonth; /*01~~12 in Dec*/
uint8_t u8RTCDayOfMonth; /*01~~31 in Dec*/
uint8_t u8RTCHour; /*fix 24Hour Format 00~~23 in Dec*/
uint8_t u8RTCMinute; /*0~~59 in Dec*/
uint8_t u8RTCSecond; /*0~~59 in Dec*/
uint8_t u8RTCWeek ; /*1~7 in Dec*/
} RTC_Information_st_t;
extern RTC_Information_st_t g_stRTCInformation;
/* RTC exported time register */
#define RTC_YEAR g_stRTCInformation.u8RTCYear
#define RTC_MONTH g_stRTCInformation.u8RTCMonth
#define RTC_DATE g_stRTCInformation.u8RTCDayOfMonth
#define RTC_HOUR g_stRTCInformation.u8RTCHour
#define RTC_MINUTE g_stRTCInformation.u8RTCMinute
#define RTC_SECOND g_stRTCInformation.u8RTCSecond
#define RTC_WEEK g_stRTCInformation.u8RTCWeek
#define RTC_LEAP_YEAR g_RTCLeapYear
extern void RTC_Pre_Init(void);
//extern void RTC_Set_Time(uint16_t day, uint8_t hour, uint8_t minute, uint8_t second);
extern void RTC_Set_Time(uint8_t year, uint8_t month, uint16_t day, uint8_t hour, uint8_t minute, uint8_t second);
extern void RTC_Get_Time(void);
extern void RTC_Backup_Time(void);
extern void Rtc_Restore_Time(void);
#endif
source/Driver/Memory/TYW_FLASH.c
View file @ f3345a2c
#include "TYW_FLASH.h"
#include "SFMA_Driver.h"
#include "stdint.h"
#include "r_dev_api.h"
#include "r_sfma_api.h"
#include "SFMA_APP.h"
#define SYSPROTCMDD1 (INT32U)(0xfff87000)
#define SYSCKSC_ISFMAS_CTL (INT32U)(0xfff85340)
#define SYSCKSC_ISFMAD_CTL (INT32U)(0xfff85380)
#define CKSC_ISFMAS_ACT (INT32U)(0xFFF85348)
#define CKSC_ISFMAD_ACT (INT32U)(0xFFF85380)
#define BUSY_TIMEOUT (INT32U)(500000ul)
#define CMNCR (INT8U)(0x00u)
#define SSLDR (INT8U)(0x04u)
#define SPBCR (INT8U)(0x08u)
#define CKDLY (INT8U)(0x50u)
#define SPODLY (INT8U)(0x68u)
#define CMNSR (INT8U)(0x48u)
#define SMCMR (INT8U)(0x24u)
#define SMENR (INT8U)(0x30u)
#define SMCR (INT8U)(0x20u)
#define SMRDR0 (INT8U)(0x38u)
#define SMRDR1 (INT8U)(0x3Cu)
#define SMWDR0 (INT8U)(0x40u)
#define SMWDR1 (INT8U)(0x44u)
#define DRCMR (INT8U)(0x10u)
#define DRENR (INT8U)(0x1Cu)
#define DRDMCR (INT8U)(0x58u)
#define DRCR (INT8U)(0x0cu)
#define DREAR (INT8U)(0x14u)
#define DRDRENR (INT8U)(0x5cu)
#define SMADR (INT8U)(0x28u)
#define SMOPR (INT8U)(0x2Cu)
#define SMDMCR (INT8U)(0x60u)
#define SMDRENR (INT8U)(0x64u)
#define DROPR (INT8U)(0x18u)
static void Flash_WaitNop(INT32U loopcount);
static void Flash_WaitNop(INT32U loopcount)
{
uint32_t i;
for (i = 0; i < loopcount; i++)
{
asm("nop");
asm("nop");
asm("nop");
asm("nop");
asm("nop");
asm("nop");
asm("nop");
asm("nop");
asm("nop");
asm("nop");
}
}
void TYW_FLASH_PreInit(void)
{
r_sfma0_Error_t ret;
uint32_t ssldr = 0x00000000u;
uint32_t spbcr = 0x00000100u;
uint32_t ckdly = 0xa5040001u;
uint32_t spodly = 0xa5000000u;
uint32_t cmncr = 0x80005000u;
uint32_t smenr = 0x00005000u;
uint32_t smcmr = 0x00ff00ffu;
uint32_t smcr = 0x00000001u;
uint32_t regval = 0;
/* ssldr = 0x00000000ul;*/
spbcr = 0x00000100ul;
ckdly = 0xa5050001ul;
spodly = 0xa5000000ul;
cmncr = 0x80505001ul;
smenr = 0x00005000ul;
smcmr = 0x00ff00fful;
smcr = 0x00000001ul;
regval = 0;
R_DEV_WRITE_PROT_REG(SYSPROTCMDD1, SYSCKSC_ISFMAS_CTL, 0X02);/*PLL1CLK 480M fPHCLK */
while (0x02u != R_DEV_READ_REG(32, CKSC_ISFMAS_ACT)) {}
R_DEV_WRITE_PROT_REG(SYSPROTCMDD1, SYSCKSC_ISFMAD_CTL, 0X03);/* 4分频率 480M/4=120M BΦ */
while (0x03u != R_DEV_READ_REG(32, SYSCKSC_ISFMAD_CTL)) {}
R_DEV_WRITE_REG(32, (0xF2FF0000ul + CMNCR), cmncr);
/* R_DEV_WRITE_REG(32, (0xF2FF0000ul + SSLDR), ssldr);*/
R_DEV_WRITE_REG(32, (0xF2FF0000ul + SPBCR), spbcr);
R_DEV_WRITE_REG(32, (0xF2FF0000ul + SPODLY), spodly);
R_DEV_WRITE_REG(32, (0xF2FF0000ul + CKDLY), ckdly);
while (0x1u != (regval & 0x1u))
{
regval = R_DEV_READ_REG(32, (0xF2FF0000ul + CMNSR));
}
}
void TYW_FLASH_DDRPreInit(SFMA_DDR_Parameter_t *DDR_Parameter)
{
r_sfma0_Error_t ret;
uint32_t ssldr = 0x00000000u;
uint32_t spbcr = 0x00000100u;
uint32_t ckdly = 0xa5040001u;
uint32_t spodly = 0xa5000000u;
uint32_t cmncr = 0x80005000u;
uint32_t smenr = 0x00005000u;
uint32_t smcmr = 0x00ff00ffu;
uint32_t smcr = 0x00000001u;
uint32_t drcr = 0ul;
uint32_t drcmr = 0ul;
uint32_t drear = 0ul;
uint32_t dropr = 0ul;
uint32_t drenr = 0ul;
uint32_t drdmcr = 0ul;
uint32_t drdrenr = 0ul;
uint32_t regval = 0;
uint32_t u32DummyCycle = 0;
/*
bit 31 MD 0 External address space read mode
bit 24 SFDE 1 Swapping is performed in 8-bit units
bit 23 22 MOIIO3 11: Output value Hi-Z
bit 21 20 MOIIO2 11: Output value Hi-Z
bit 19 18 MOIIO1 11: Output value Hi-Z
bit 17 16 MOIIO0 11: Output value Hi-Z
bit 15 14 IO3FV 11: Output value Hi-Z
bit 13 12 IO2FV 11: Output value Hi-Z
bit 9 8 IO0FV 11: Output value Hi-Z
bit 6 CPHAT Data transmission starts at even edge during DDR transfer.
bit 5 CPHAR Data transmission starts at even edge during DDR transfer.
bit 4 SSLP Active low SPBSSL signal
bit 3 cpol SPBCLK output is 0 during SPBSSL negation period.
bit 0 1 BSZ 2 memories
*/
cmncr = 0x01FFF301UL;/* CONFIRMED Fix */
/* ssldr = 0x00000000ul;*/
spbcr = 0x00000100ul;/* CONFIRMED Fix 120M/(2*1*1)=60M */
spodly = 0xa5000000ul;/* CONFIRMED Fix */
/* fphclk/fbΦ =480/120=4 */
/*
stepsize = 180/4 =45°
max step =360/45-2=6
maxshift = 6*45=270°
*/
ckdly = 0xa5050000ul;/* CONFIRMED Modify but fix */
smcmr = 0x00ee0000ul;/* do not care */
smenr = 0x00025000ul;/* do not care */
smcr = 0x00ee0000ul;/* do not care */
/*
• Set the normal read or burst read operation.
• Set the SPBSSL negation during burst read operation.
• Set the burst length during burst read operation
*/
/*
bit 31-29 0 BFM Burst length depends on the access size. Further the cache is flushed at each cycle.
BIT 24 SSLN 0 Asserted SPBSSL can be negated by writing 1 to this bit when both the RBE and SSLE bits are 1.
bit 19-16 RBURST F 1111: 16 continuous data units
bit 9 RCF 1 When 1 is written to this bit, all the entries in the read cache are cleared. This bit is always read as 0.
bit 8 RBE 1 read cache is enabled, and as many data units as the burst count specified in RBURST[3:0] bits is read
BIT 0 SSLE 1 SPBSSL is negated when the accessed address is not continuous with the previously transferred address
*/
drcr = 0x000f0301ul;/* CONFIRMED Fix */
/*
• Set the command/optional command when reading
*/
/*
BIT 23-16 CMD 0XED
BIT 7-0 OCMD 0X00
*/
drcmr = 0x00000000ul; /* CONFIRMED Modify */
drcmr |= ((uint32_t)(DDR_Parameter->DTR_CMD)) << 16; /* CONFIRMED Modify */
/*
• Set the option data when reading
*/
dropr = 0x00000000UL;/* CONFIRMED Modify */
dropr |= ((uint32_t)(DDR_Parameter->DTR_MF0_7)) << 24; /* CONFIRMED Modify */
/*
• Enable the transfer data.
• Set the transfer data size in bit units
BIT 31 30 CDB 00: 1 bit
BIT 29 28 OCDB 00: 1 bit
BIT 25 24 ADB 10: 4 bits
BIT 21 20 OPDB 10: 4 bits
BIT 17 16 DRDB 10: 4 bits
BIT 15 DME 1: Dummy cycle insertion enabled
BIT 14 CDE 1: Command output enabled
BIT 12 OCDE 0: Optional command output disable
BIT 11-8 ADE 1111: Address[32:1]
BIT 7-4 OPDE 0000: OPD3
*/
drenr = 0x0222CF80ul; /* CONFIRMED Fix */
/*
• Set the address when the serial flash address is output in 32-bit units.
(only when DRENR.ADE[3] = 1)
bit 23-16 EAV 00000000
bit 2-0 EAC 100: External address bits [28:0] enabled
*/
drear = 0x00000004ul;/* CONFIRMED Fix */
/*
• Set the dummy cycle size in bit units.
• Set the number of dummy cycles.
*/
/*
BIT 17 16 DMDB 2: 4 bits
BIT 2-0 DMCYC 110: 7 cycles
*/
drdmcr = 0x00020000ul; /* CONFIRMED Modify */
u32DummyCycle = DDR_Parameter->DTR_DummyCycle;
if (u32DummyCycle != 0)
{
u32DummyCycle = u32DummyCycle - 1;
}
drdmcr |= u32DummyCycle; /* CONFIRMED Modify */
/*
bit 8 ADDRE 1: DDR transfe
bit 4 OPDRE 1: DDR transfer
bit 1 DRDRE 1: DDR transfer
*/
drdrenr = 0x00000111ul;/* CONFIRMED FIX */
regval = 0;
R_DEV_WRITE_REG(32, (0xF2FF0000ul + CMNCR ), cmncr);
/* R_DEV_WRITE_REG(32, (0xF2FF0000ul + SSLDR ), ssldr);*/
R_DEV_WRITE_REG(32, (0xF2FF0000ul + SPBCR ), spbcr);
R_DEV_WRITE_REG(32, (0xF2FF0000ul + SPODLY ), spodly);
R_DEV_WRITE_REG(32, (0xF2FF0000ul + CKDLY ), ckdly);
R_DEV_WRITE_REG(32, (0xF2FF0000ul + SMCMR ), smcmr);
R_DEV_WRITE_REG(32, (0xF2FF0000ul + SMENR ), smenr);
R_DEV_WRITE_REG(32, (0xF2FF0000ul + SMCR ), smcr );
R_DEV_WRITE_REG(32, (0xF2FF0000ul + DRCR ), drcr);
R_DEV_WRITE_REG(32, (0xF2FF0000ul + DRCMR ), drcmr);
R_DEV_WRITE_REG(32, (0xF2FF0000ul + DREAR ), drear);
R_DEV_WRITE_REG(32, (0xF2FF0000ul + DROPR ), dropr);
R_DEV_WRITE_REG(32, (0xF2FF0000ul + DRENR ), drenr);
R_DEV_WRITE_REG(32, (0xF2FF0000ul + DRDMCR ), drdmcr);
R_DEV_WRITE_REG(32, (0xF2FF0000ul + DRDRENR), drdrenr);
while (0x1u != (regval & 0x1u))
{
regval = R_DEV_READ_REG(32, (0xF2FF0000ul + CMNSR));
}
}
void TYW_FLASH_Init(void)
{
uint32_t TEMP[2];
FLASH_MANUFACTURER_ID_t FlashType;
SFMA_DDR_Parameter_t SFMA_Parameter;
uint32_t i_count;
i_count=0;
Total_Begin:
i_count++;
if(i_count>=20)
{
goto End_Begin;
}
Flash_WaitNop(60);
TYW_FLASH_PreInit();
FlashType = SPI_NOR_Init();
switch (FlashType)
{
case SPANSION:
break;
case WINBOND:
SFMA_Parameter.DTR_CMD = 0xED;
SFMA_Parameter.DTR_MF0_7 = 0xFF;
SFMA_Parameter.DTR_DummyCycle = 0x07;
break;
case ISSI:
SFMA_Parameter.DTR_CMD = 0xEE;
SFMA_Parameter.DTR_MF0_7 = 0xFF;
SFMA_Parameter.DTR_DummyCycle = 0x06;
break;
case Macronix:
break;
case GIGADEVICE:
break;
default:
break;
}
TYW_FLASH_DDRPreInit(&SFMA_Parameter);
Flash_WaitNop(60);
TEMP[0] = ((*((volatile uint32_t *)((0x10000000u)))));
TEMP[1] = ((*((volatile uint32_t *)((0x10000004u)))));
if ((TEMP[0] != 0x50415247) && (TEMP[1] != 0x50415f45))
{
goto Total_Begin;
}
End_Begin:
i_count=0;
}
#include "TYW_FLASH.h"
#include "SFMA_Driver.h"
#include "stdint.h"
#include "r_dev_api.h"
#include "r_sfma_api.h"
#include "SFMA_APP.h"
#include "Watchdog.h"
#include "GPIO.h"
#include "RTC.h"
#include "rh850_macros.h"
#define SYSPROTCMDD1 (INT32U)(0xfff87000)
#define SYSCKSC_ISFMAS_CTL (INT32U)(0xfff85340)
#define SYSCKSC_ISFMAD_CTL (INT32U)(0xfff85380)
#define CKSC_ISFMAS_ACT (INT32U)(0xFFF85348)
#define CKSC_ISFMAD_ACT (INT32U)(0xFFF85380)
#define BUSY_TIMEOUT (INT32U)(500000ul)
#define CMNCR (INT8U)(0x00u)
#define SSLDR (INT8U)(0x04u)
#define SPBCR (INT8U)(0x08u)
#define CKDLY (INT8U)(0x50u)
#define SPODLY (INT8U)(0x68u)
#define CMNSR (INT8U)(0x48u)
#define SMCMR (INT8U)(0x24u)
#define SMENR (INT8U)(0x30u)
#define SMCR (INT8U)(0x20u)
#define SMRDR0 (INT8U)(0x38u)
#define SMRDR1 (INT8U)(0x3Cu)
#define SMWDR0 (INT8U)(0x40u)
#define SMWDR1 (INT8U)(0x44u)
#define DRCMR (INT8U)(0x10u)
#define DRENR (INT8U)(0x1Cu)
#define DRDMCR (INT8U)(0x58u)
#define DRCR (INT8U)(0x0cu)
#define DREAR (INT8U)(0x14u)
#define DRDRENR (INT8U)(0x5cu)
#define SMADR (INT8U)(0x28u)
#define SMOPR (INT8U)(0x2Cu)
#define SMDMCR (INT8U)(0x60u)
#define SMDRENR (INT8U)(0x64u)
#define DROPR (INT8U)(0x18u)
static void Flash_WaitNop(INT32U loopcount);
static void Flash_WaitNop(INT32U loopcount)
{
uint32_t i;
WDT_Clear();
for (i = 0; i < loopcount; i++)
{
WDT_Clear();
asm("nop");
asm("nop");
asm("nop");
asm("nop");
asm("nop");
asm("nop");
asm("nop");
asm("nop");
asm("nop");
asm("nop");
}
}
void TYW_FLASH_PreInit(void)
{
uint16_t WhileCnts = 0;
r_sfma0_Error_t ret;
uint32_t ssldr = 0x00000000u;
uint32_t spbcr = 0x00000100u;
uint32_t ckdly = 0xa5040001u;
uint32_t spodly = 0xa5000000u;
uint32_t cmncr = 0x80005000u;
uint32_t smenr = 0x00005000u;
uint32_t smcmr = 0x00ff00ffu;
uint32_t smcr = 0x00000001u;
uint32_t regval = 0;
/* ssldr = 0x00000000ul;*/
spbcr = 0x00000100ul;
ckdly = 0xa5050001ul;
spodly = 0xa5000000ul;
cmncr = 0x80505001ul;
smenr = 0x00005000ul;
smcmr = 0x00ff00fful;
smcr = 0x00000001ul;
regval = 0;
R_DEV_WRITE_PROT_REG(SYSPROTCMDD1, SYSCKSC_ISFMAS_CTL, 0X02);/*PLL1CLK 480M fPHCLK */
while (0x02u != R_DEV_READ_REG(32, CKSC_ISFMAS_ACT)) {}
R_DEV_WRITE_PROT_REG(SYSPROTCMDD1, SYSCKSC_ISFMAD_CTL, 0X03);/* 4分频率 480M/4=120M BΦ */
while (0x03u != R_DEV_READ_REG(32, SYSCKSC_ISFMAD_CTL)) {}
regval = R_DEV_READ_REG(32, (0xF2FF0000ul + CMNSR));
if (0x1u != (regval & 0x1u)) {
RTC_Backup_Time();
TestBackupRam = 0xaabbccddu;
hardware_reset();
}
R_DEV_WRITE_REG(32, (0xF2FF0000ul + CMNCR), cmncr);
/* R_DEV_WRITE_REG(32, (0xF2FF0000ul + SSLDR), ssldr);*/
R_DEV_WRITE_REG(32, (0xF2FF0000ul + SPBCR), spbcr);
R_DEV_WRITE_REG(32, (0xF2FF0000ul + SPODLY), spodly);
R_DEV_WRITE_REG(32, (0xF2FF0000ul + CKDLY), ckdly);
WhileCnts = 0;
while (0x1u != (regval & 0x1u))
{
if (WhileCnts++ >= 100) {
RTC_Backup_Time();
TestBackupRam = 0xaabbccddu;
hardware_reset();
}
WDT_Clear();
regval = R_DEV_READ_REG(32, (0xF2FF0000ul + CMNSR));
}
}
void TYW_FLASH_DDRPreInit(SFMA_DDR_Parameter_t *DDR_Parameter)
{
uint16_t WhileCnts = 0;
r_sfma0_Error_t ret;
uint32_t ssldr = 0x00000000u;
uint32_t spbcr = 0x00000100u;
uint32_t ckdly = 0xa5040001u;
uint32_t spodly = 0xa5000000u;
uint32_t cmncr = 0x80005000u;
uint32_t smenr = 0x00005000u;
uint32_t smcmr = 0x00ff00ffu;
uint32_t smcr = 0x00000001u;
uint32_t drcr = 0ul;
uint32_t drcmr = 0ul;
uint32_t drear = 0ul;
uint32_t dropr = 0ul;
uint32_t drenr = 0ul;
uint32_t drdmcr = 0ul;
uint32_t drdrenr = 0ul;
uint32_t regval = 0;
uint32_t u32DummyCycle = 0;
/*
bit 31 MD 0 External address space read mode
bit 24 SFDE 1 Swapping is performed in 8-bit units
bit 23 22 MOIIO3 11: Output value Hi-Z
bit 21 20 MOIIO2 11: Output value Hi-Z
bit 19 18 MOIIO1 11: Output value Hi-Z
bit 17 16 MOIIO0 11: Output value Hi-Z
bit 15 14 IO3FV 11: Output value Hi-Z
bit 13 12 IO2FV 11: Output value Hi-Z
bit 9 8 IO0FV 11: Output value Hi-Z
bit 6 CPHAT Data transmission starts at even edge during DDR transfer.
bit 5 CPHAR Data transmission starts at even edge during DDR transfer.
bit 4 SSLP Active low SPBSSL signal
bit 3 cpol SPBCLK output is 0 during SPBSSL negation period.
bit 0 1 BSZ 2 memories
*/
cmncr = 0x01FFF301UL;/* CONFIRMED Fix */
/* ssldr = 0x00000000ul;*/
spbcr = 0x00000100ul;/* CONFIRMED Fix 120M/(2*1*1)=60M */
spodly = 0xa5000000ul;/* CONFIRMED Fix */
/* fphclk/fbΦ =480/120=4 */
/*
stepsize = 180/4 =45°
max step =360/45-2=6
maxshift = 6*45=270°
*/
ckdly = 0xa5050000ul;/* CONFIRMED Modify but fix */
smcmr = 0x00ee0000ul;/* do not care */
smenr = 0x00025000ul;/* do not care */
smcr = 0x00ee0000ul;/* do not care */
/*
• Set the normal read or burst read operation.
• Set the SPBSSL negation during burst read operation.
• Set the burst length during burst read operation
*/
/*
bit 31-29 0 BFM Burst length depends on the access size. Further the cache is flushed at each cycle.
BIT 24 SSLN 0 Asserted SPBSSL can be negated by writing 1 to this bit when both the RBE and SSLE bits are 1.
bit 19-16 RBURST F 1111: 16 continuous data units
bit 9 RCF 1 When 1 is written to this bit, all the entries in the read cache are cleared. This bit is always read as 0.
bit 8 RBE 1 read cache is enabled, and as many data units as the burst count specified in RBURST[3:0] bits is read
BIT 0 SSLE 1 SPBSSL is negated when the accessed address is not continuous with the previously transferred address
*/
drcr = 0x000f0301ul;/* CONFIRMED Fix */
/*
• Set the command/optional command when reading
*/
/*
BIT 23-16 CMD 0XED
BIT 7-0 OCMD 0X00
*/
drcmr = 0x00000000ul; /* CONFIRMED Modify */
drcmr |= ((uint32_t)(DDR_Parameter->DTR_CMD)) << 16; /* CONFIRMED Modify */
/*
• Set the option data when reading
*/
dropr = 0x00000000UL;/* CONFIRMED Modify */
dropr |= ((uint32_t)(DDR_Parameter->DTR_MF0_7)) << 24; /* CONFIRMED Modify */
/*
• Enable the transfer data.
• Set the transfer data size in bit units
BIT 31 30 CDB 00: 1 bit
BIT 29 28 OCDB 00: 1 bit
BIT 25 24 ADB 10: 4 bits
BIT 21 20 OPDB 10: 4 bits
BIT 17 16 DRDB 10: 4 bits
BIT 15 DME 1: Dummy cycle insertion enabled
BIT 14 CDE 1: Command output enabled
BIT 12 OCDE 0: Optional command output disable
BIT 11-8 ADE 1111: Address[32:1]
BIT 7-4 OPDE 0000: OPD3
*/
drenr = 0x0222CF80ul; /* CONFIRMED Fix */
/*
• Set the address when the serial flash address is output in 32-bit units.
(only when DRENR.ADE[3] = 1)
bit 23-16 EAV 00000000
bit 2-0 EAC 100: External address bits [28:0] enabled
*/
drear = 0x00000004ul;/* CONFIRMED Fix */
/*
• Set the dummy cycle size in bit units.
• Set the number of dummy cycles.
*/
/*
BIT 17 16 DMDB 2: 4 bits
BIT 2-0 DMCYC 110: 7 cycles
*/
drdmcr = 0x00020000ul; /* CONFIRMED Modify */
u32DummyCycle = DDR_Parameter->DTR_DummyCycle;
if (u32DummyCycle != 0)
{
u32DummyCycle = u32DummyCycle - 1;
}
drdmcr |= u32DummyCycle; /* CONFIRMED Modify */
/*
bit 8 ADDRE 1: DDR transfe
bit 4 OPDRE 1: DDR transfer
bit 1 DRDRE 1: DDR transfer
*/
drdrenr = 0x00000111ul;/* CONFIRMED FIX */
regval = R_DEV_READ_REG(32, (0xF2FF0000ul + CMNSR));
if (0x1u != (regval & 0x1u)) {
RTC_Backup_Time();
TestBackupRam = 0xaabbccddu;
hardware_reset();
}
R_DEV_WRITE_REG(32, (0xF2FF0000ul + CMNCR ), cmncr);
/* R_DEV_WRITE_REG(32, (0xF2FF0000ul + SSLDR ), ssldr);*/
R_DEV_WRITE_REG(32, (0xF2FF0000ul + SPBCR ), spbcr);
R_DEV_WRITE_REG(32, (0xF2FF0000ul + SPODLY ), spodly);
R_DEV_WRITE_REG(32, (0xF2FF0000ul + CKDLY ), ckdly);
R_DEV_WRITE_REG(32, (0xF2FF0000ul + SMCMR ), smcmr);
R_DEV_WRITE_REG(32, (0xF2FF0000ul + SMENR ), smenr);
R_DEV_WRITE_REG(32, (0xF2FF0000ul + SMCR ), smcr );
R_DEV_WRITE_REG(32, (0xF2FF0000ul + DRCR ), drcr);
R_DEV_WRITE_REG(32, (0xF2FF0000ul + DRCMR ), drcmr);
R_DEV_WRITE_REG(32, (0xF2FF0000ul + DREAR ), drear);
R_DEV_WRITE_REG(32, (0xF2FF0000ul + DROPR ), dropr);
R_DEV_WRITE_REG(32, (0xF2FF0000ul + DRENR ), drenr);
R_DEV_WRITE_REG(32, (0xF2FF0000ul + DRDMCR ), drdmcr);
R_DEV_WRITE_REG(32, (0xF2FF0000ul + DRDRENR), drdrenr);
WhileCnts = 0;
while (0x1u != (regval & 0x1u))
{
if (WhileCnts++ >= 100) {
RTC_Backup_Time();
TestBackupRam = 0xaabbccddu;
hardware_reset();
}
WDT_Clear();
regval = R_DEV_READ_REG(32, (0xF2FF0000ul + CMNSR));
}
}
#pragma ghs section bss=".NonInitArea"
uint32_t i_count;
uint32_t TestBackupRam;
#pragma ghs section bss=default
void TYW_FLASH_Init(void)
{
uint32_t TEMP[2];
FLASH_MANUFACTURER_ID_t FlashType;
SFMA_DDR_Parameter_t SFMA_Parameter;
i_count=0;
Total_Begin:
i_count++;
if(i_count>=20)
{
goto End_Begin;
}
Flash_WaitNop(1000);
TYW_FLASH_PreInit();
FlashType = SPI_NOR_Init();
switch (FlashType)
{
case SPANSION:
SFMA_Parameter.DTR_CMD = 0xEE;
SFMA_Parameter.DTR_MF0_7 = 0xff;
SFMA_Parameter.DTR_DummyCycle = 0x08;
break;
case WINBOND:
SFMA_Parameter.DTR_CMD = 0xED;
SFMA_Parameter.DTR_MF0_7 = 0xFF;
SFMA_Parameter.DTR_DummyCycle = 0x07;
break;
case ISSI:
SFMA_Parameter.DTR_CMD = 0xEE;
SFMA_Parameter.DTR_MF0_7 = 0xFF;
SFMA_Parameter.DTR_DummyCycle = 0x06;
break;
case Macronix:
break;
case GIGADEVICE:
break;
default:
break;
}
TYW_FLASH_DDRPreInit(&SFMA_Parameter);
Flash_WaitNop(1000);
TEMP[0] = ((*((volatile uint32_t *)((0x10000000u)))));
TEMP[1] = ((*((volatile uint32_t *)((0x10000004u)))));
if ((TEMP[0] != 0x50415247) || (TEMP[1] != 0x50415f45))
{
goto Total_Begin;
}
End_Begin:
//i_count=0;
}
source/Driver/Memory/TYW_FLASH.h
View file @ f3345a2c
#ifndef TYW_FLASH_H
#define TYW_FLASH_H
#include"stdint.h"
typedef enum
{
R_SFMA0_ERR_OK = 0,
R_SFMA0_ERR_NG,
R_SFMA0_ERR_PARAM_INCORRECT,
R_SFMA0_ERR_RANGE_UNIT,
R_SFMA0_ERR_RANGE_PARAM,
R_SFMA0_ERR_NOT_ACCEPTABLE,
R_SFMA0_ERR_FATAL_OS,
R_SFMA0_ERR_FATAL_HW,
R_SFMA0_ERR_NOT_SUPPORT_CLOCK,
R_SFMA0_ERR_NOT_SUPPORT_TRANSFER,
R_SFMA0_ERR_SFLASH_PROTECTED,
R_SFMA0_ERR_NOT_SUPPORTED
} r_sfma0_Error_t;
typedef struct
{
uint8_t DTR_CMD;
uint8_t DTR_MF0_7;
uint8_t DTR_DummyCycle;
}SFMA_DDR_Parameter_t;
void TYW_FLASH_Init(void);
void TYW_FLASH_PreInit(void);
void TYW_FLASH_DDRPreInit(SFMA_DDR_Parameter_t *DDR_Parameter);
#ifndef TYW_FLASH_H
#define TYW_FLASH_H
//#include"stdint.h"
#include "r_typedefs.h"
typedef enum
{
R_SFMA0_ERR_OK = 0,
R_SFMA0_ERR_NG,
R_SFMA0_ERR_PARAM_INCORRECT,
R_SFMA0_ERR_RANGE_UNIT,
R_SFMA0_ERR_RANGE_PARAM,
R_SFMA0_ERR_NOT_ACCEPTABLE,
R_SFMA0_ERR_FATAL_OS,
R_SFMA0_ERR_FATAL_HW,
R_SFMA0_ERR_NOT_SUPPORT_CLOCK,
R_SFMA0_ERR_NOT_SUPPORT_TRANSFER,
R_SFMA0_ERR_SFLASH_PROTECTED,
R_SFMA0_ERR_NOT_SUPPORTED
} r_sfma0_Error_t;
typedef struct
{
uint8_t DTR_CMD;
uint8_t DTR_MF0_7;
uint8_t DTR_DummyCycle;
}SFMA_DDR_Parameter_t;
void TYW_FLASH_Init(void);
void TYW_FLASH_PreInit(void);
void TYW_FLASH_DDRPreInit(SFMA_DDR_Parameter_t *DDR_Parameter);
extern uint32_t TestBackupRam;
#endif
\ No newline at end of file
source/System/d1mx.ld
View file @ f3345a2c
/*===========================================================================*/
/* Module = dr7f701412.ld */
/* Version = E1.00f */
/* extracted from device file dr7f701412.dvf */
/* by DeFiXRH850 0.7.2.3 */
/*===========================================================================*/
/* COPYRIGHT */
/*===========================================================================*/
/* Copyright (c) 2014 by Renesas Electronics Europe GmbH, */
/* a company of the Renesas Electronics Corporation */
/*===========================================================================*/
/* Purpose: Template of linker directive file */
/* */
/*===========================================================================*/
/* */
/* Warranty Disclaimer */
/* */
/* Because the Product(s) is licensed free of charge, there is no warranty */
/* of any kind whatsoever and expressly disclaimed and excluded by Renesas, */
/* either expressed or implied, including but not limited to those for */
/* non-infringement of intellectual property, merchantability and/or */
/* fitness for the particular purpose. */
/* Renesas shall not have any obligation to maintain, service or provide bug */
/* fixes for the supplied Product(s) and/or the Application. */
/* */
/* Each User is solely responsible for determining the appropriateness of */
/* using the Product(s) and assumes all risks associated with its exercise */
/* of rights under this Agreement, including, but not limited to the risks */
/* and costs of program errors, compliance with applicable laws, damage to */
/* or loss of data, programs or equipment, and unavailability or */
/* interruption of operations. */
/* */
/* Limitation of Liability */
/* */
/* In no event shall Renesas be liable to the User for any incidental, */
/* consequential, indirect, or punitive damage (including but not limited */
/* to lost profits) regardless of whether such liability is based on breach */
/* of contract, tort, strict liability, breach of warranties, failure of */
/* essential purpose or otherwise and even if advised of the possibility of */
/* such damages. Renesas shall not be liable for any services or products */
/* provided by third party vendors, developers or consultants identified or */
/* referred to the User by Renesas in connection with the Product(s) and/or */
/* the Application. */
/* */
/*===========================================================================*/
/* Environment: */
/* Device: R7F701412 */
/* IDE: GHS Multi for V800 V6.xx or later */
/*===========================================================================*/
CONSTANTS
{
zero_start = 0xffff8000
}
MEMORY
{
iROM_0 : ORIGIN = 0x00000000, LENGTH = 5120k
iRAM_0 : ORIGIN = 0xFEB80000, LENGTH = 512k /* RAM addres space seen by external bus masters */
iRAM_1 : ORIGIN = 0xFED80000, LENGTH = 512k /* local RAM address space */
iRAM_R : ORIGIN = 0x3FCE4000, LENGTH = 16k
}
SECTIONS
{
/* Start of internal ROM area (iROM_0) */
.intvect :>iROM_0 /* start of interrupt vector */
.intvect_end 0x00000600 :>. /* end of interrupt vector */
.text align(4) :>. /* program code area */
.rozdata :>. /* constant datas in ZDA area */
.robase align(4) :>. /* initialize textpointer TP for SDA addressing */
.rosdata align(4) :>. /* constant datas in SDA area */
.rodata align(4) :>. /* constant datas in normal area */
.fixaddr align(4) :>. /* ghs internal (compiler) */
.fixtype align(4) :>. /* ghs internal (compiler) */
.secinfo align(4) :>. /* ghs internal (runtime library) */
.syscall align(4) :>. /* ghs internal (linker) */
.romdata ROM(.data) :>. /* constant data to initialize variables (copied to RAM at startup)*/
.romzdata ROM(.zdata) :>. /* constant data to initialize variables in ZDA area (copied to RAM at startup)*/
.romsdata ROM(.sdata) :>. /* constant data to initialize variables in SDA area (copied to RAM at startup)*/
.romtdata ROM(.tdata) :>. /* constant data to initialize variables in TDA area (copied to RAM at startup)*/
.ROM.ramfunc ROM(.ramfunc) :>. /* program code to be copied to RAM (copied to RAM at startup) */
/* Start of internal RAM area (iRAM) */
.data :>iRAM_0 /* initialized data */
.bss align(4) :>. /* zero initialized data*/
//.sdabase align(4) :>. /* initialize globalpointer GP for SDA addressing */
.sda_start align(4) :>.
.sdata align(4) :>. /* initialized data in SDA area*/
.sbss align(4) :>. /* zero initialized data in SDA area*/
.sda_end align(4) :>.
.zdata align(4) :>. /* initialized data in ZDA area*/
.zbss align(4) :>. /* zero initialized data in ZDA area*/
.tdata align(4) MAX_SIZE(0x0100) :>. /* initialized and zero-initialized data in TDA area */
.ramfunc align(4) :>. /* program code in RAM area */
.stack align(4) pad(0x4000) :>. /* definition of stack size */
.heapbase align(4) :>.
.heap align(4)
pad(MEMENDADDR(iRAM_0)-addr(.heapbase))
NOCLEAR :>. /* definition of heap size */
/* Start of internal retention RAM area (iRAM_R) */
.rdata align(4) :>iRAM_R /* user defined segment for for initialized data located in retention RAM */
.rbss align(4) :>. /* user defined segment for zero initialized data located in retention RAM */
.NonInitArea align(4) NOCLEAR :>. /* non initalised are in the BURAM */
/* Symbols for compiler references */
___ghs_romstart = MEMADDR(iROM_0);
___ghs_romend = MEMENDADDR(iROM_0);
___ghs_ramstart = MEMADDR(iRAM_0);
___ghs_ramend = MEMENDADDR(iRAM_0);
___ghs_rramstart = MEMADDR(iRAM_R);
___ghs_rramend = MEMENDADDR(iRAM_R);
}
/*===========================================================================*/
/* End of File */
/*===========================================================================*/
/*===========================================================================*/
/* Module = dr7f701412.ld */
/* Version = E1.00f */
/* extracted from device file dr7f701412.dvf */
/* by DeFiXRH850 0.7.2.3 */
/*===========================================================================*/
/* COPYRIGHT */
/*===========================================================================*/
/* Copyright (c) 2014 by Renesas Electronics Europe GmbH, */
/* a company of the Renesas Electronics Corporation */
/*===========================================================================*/
/* Purpose: Template of linker directive file */
/* */
/*===========================================================================*/
/* */
/* Warranty Disclaimer */
/* */
/* Because the Product(s) is licensed free of charge, there is no warranty */
/* of any kind whatsoever and expressly disclaimed and excluded by Renesas, */
/* either expressed or implied, including but not limited to those for */
/* non-infringement of intellectual property, merchantability and/or */
/* fitness for the particular purpose. */
/* Renesas shall not have any obligation to maintain, service or provide bug */
/* fixes for the supplied Product(s) and/or the Application. */
/* */
/* Each User is solely responsible for determining the appropriateness of */
/* using the Product(s) and assumes all risks associated with its exercise */
/* of rights under this Agreement, including, but not limited to the risks */
/* and costs of program errors, compliance with applicable laws, damage to */
/* or loss of data, programs or equipment, and unavailability or */
/* interruption of operations. */
/* */
/* Limitation of Liability */
/* */
/* In no event shall Renesas be liable to the User for any incidental, */
/* consequential, indirect, or punitive damage (including but not limited */
/* to lost profits) regardless of whether such liability is based on breach */
/* of contract, tort, strict liability, breach of warranties, failure of */
/* essential purpose or otherwise and even if advised of the possibility of */
/* such damages. Renesas shall not be liable for any services or products */
/* provided by third party vendors, developers or consultants identified or */
/* referred to the User by Renesas in connection with the Product(s) and/or */
/* the Application. */
/* */
/*===========================================================================*/
/* Environment: */
/* Device: R7F701412 */
/* IDE: GHS Multi for V800 V6.xx or later */
/*===========================================================================*/
CONSTANTS
{
zero_start = 0xffff8000
}
MEMORY
{
iROM_0 : ORIGIN = 0x00200400, LENGTH = 2048k
iRAM_0 : ORIGIN = 0xFEB80000, LENGTH = 512k /* RAM addres space seen by external bus masters */
iRAM_1 : ORIGIN = 0xFED80000, LENGTH = 512k /* local RAM address space */
iRAM_R0 : ORIGIN = 0x3FCE4000, LENGTH = 1k
iRAM_R : ORIGIN = 0x3FCE4400, LENGTH = 16k
}
SECTIONS
{
/* Start of internal ROM area (iROM_0) */
.intvect :>iROM_0 /* start of interrupt vector */
.intvect_end 0x200a00 :>. /* end of interrupt vector */
.text align(4) :>. /* program code area */
.rozdata :>. /* constant datas in ZDA area */
.robase align(4) :>. /* initialize textpointer TP for SDA addressing */
.rosdata align(4) :>. /* constant datas in SDA area */
.rodata align(4) :>. /* constant datas in normal area */
.fixaddr align(4) :>. /* ghs internal (compiler) */
.fixtype align(4) :>. /* ghs internal (compiler) */
.secinfo align(4) :>. /* ghs internal (runtime library) */
.syscall align(4) :>. /* ghs internal (linker) */
.romdata ROM(.data) :>. /* constant data to initialize variables (copied to RAM at startup)*/
.romzdata ROM(.zdata) :>. /* constant data to initialize variables in ZDA area (copied to RAM at startup)*/
.romsdata ROM(.sdata) :>. /* constant data to initialize variables in SDA area (copied to RAM at startup)*/
.romtdata ROM(.tdata) :>. /* constant data to initialize variables in TDA area (copied to RAM at startup)*/
.ROM.ramfunc ROM(.ramfunc) :>. /* program code to be copied to RAM (copied to RAM at startup) */
/* Start of internal RAM area (iRAM) */
.data :>iRAM_0 /* initialized data */
.bss align(4) :>. /* zero initialized data*/
//.sdabase align(4) :>. /* initialize globalpointer GP for SDA addressing */
.sda_start align(4) :>.
.sdata align(4) :>. /* initialized data in SDA area*/
.sbss align(4) :>. /* zero initialized data in SDA area*/
.sda_end align(4) :>.
.zdata align(4) :>. /* initialized data in ZDA area*/
.zbss align(4) :>. /* zero initialized data in ZDA area*/
.tdata align(4) MAX_SIZE(0x0100) :>. /* initialized and zero-initialized data in TDA area */
.ramfunc align(4) :>. /* program code in RAM area */
.stack align(4) pad(0x4000) :>. /* definition of stack size */
.heapbase align(4) :>.
.heap align(4)
pad(MEMENDADDR(iRAM_0)-addr(.heapbase))
NOCLEAR :>. /* definition of heap size */
/* Start of internal retention RAM area (iRAM_R) */
.absinitarea align(4) NOCLEAR :>iRAM_R0
.rdata align(4) :>iRAM_R /* user defined segment for for initialized data located in retention RAM */
.rbss align(4) :>. /* user defined segment for zero initialized data located in retention RAM */
.NonInitArea align(4) NOCLEAR :>. /* non initalised are in the BURAM */
/* Symbols for compiler references */
___ghs_romstart = MEMADDR(iROM_0);
___ghs_romend = MEMENDADDR(iROM_0);
___ghs_ramstart = MEMADDR(iRAM_0);
___ghs_ramend = MEMENDADDR(iRAM_0);
___ghs_rramstart = MEMADDR(iRAM_R);
___ghs_rramend = MEMENDADDR(iRAM_R);
}
/*===========================================================================*/
/* End of File */
/*===========================================================================*/
source/System/init.c
View file @ f3345a2c
......@@ -82,6 +82,11 @@ void Sys_Startup_Pre_Init(void)
* \attention
* \retval None
******************************************************************************/
uint8_t u8ResetFlag = 0;
extern uint32_t u32ResetFlag;
extern uint32_t TestBackupRam;
void Sys_Startup_Init(void)
{
Clock_Init();
......@@ -97,7 +102,7 @@ void Sys_Startup_Init(void)
CPU_Init();
RTC_Init();
//RTC_Init();
Sys_Tick_Timer_Start();
/*COM_CAN_Init(); Ô­CAN³õʼ»¯Î»ÖÃ*/
......@@ -117,10 +122,26 @@ void Sys_Startup_Init(void)
ReadDTCEOLValue_Meter_K_LINE();
d_printf("Init complete!\n");
InitSeriFlashExternReadMode();
//APP_Startup_Init(Clock_Get_Startup_Mode());
u8ResetFlag = Clock_Get_Startup_Mode();
if (u32ResetFlag != 0xA55AA55AUL)
{
u8ResetFlag = 0;
}
else
{
if ((u8ResetFlag == 0) && (TestBackupRam == 0xaabbccddu))
{
u8ResetFlag = 1;
Rtc_Restore_Time();
}
}
/*30电初始化*/
APP_Startup_Init(u8ResetFlag);
TestBackupRam = 0x11223344UL;
InitSeriFlashExternReadMode();
/*30电数据初始化*/
APP_Startup_Init(Clock_Get_Startup_Mode());
/*外发要用到EEP数据，位置移动*/
COM_CAN_Init();
Gfx_Sys_Start();
......
source/System/main.c
View file @ f3345a2c
#include "r_typedefs.h"
#include "sys_scheduler.h"
#include "Watchdog.h"
extern uint32_t u32ResetFlag;
int main(void)
{
Sys_Init();
while (1U)
{
u32ResetFlag = 0xA55AA55AUL;
Sys_Scheduling_Service();
WDT_Clear();
}
}
}
\ No newline at end of file
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment