Skip to content

H
haoJin750TFT
Commit f2cae379 authored by 李延凯's avatar 李延凯
Browse files
Options

feat: 修改启动地址, 修改选项字节地址

parent 6e32a063
Show whitespace changes
Inline Side-by-side
Showing with 22 additions and 6293 deletions
Firmware/Project/Cmsemicon/BAT32A279/MDK_ARM/HaoJin750TFT.uvprojx
View file @ f2cae379
...@@ -211,7 +211,7 @@ ...@@ -211,7 +211,7 @@
<Ra2Chk>0</Ra2Chk> <Ra2Chk>0</Ra2Chk>
<Ra3Chk>0</Ra3Chk> <Ra3Chk>0</Ra3Chk>
<Im1Chk>1</Im1Chk> <Im1Chk>1</Im1Chk>
<Im2Chk>0</Im2Chk> <Im2Chk>1</Im2Chk>
<OnChipMemories> <OnChipMemories>
<Ocm1> <Ocm1>
<Type>0</Type> <Type>0</Type>
...@@ -275,8 +275,8 @@ ...@@ -275,8 +275,8 @@
</OCR_RVCT3> </OCR_RVCT3>
<OCR_RVCT4> <OCR_RVCT4>
<Type>1</Type> <Type>1</Type>
<StartAddress>0x0</StartAddress> <StartAddress>0xc400</StartAddress>
<Size>0x80000</Size> <Size>0x73c00</Size>
</OCR_RVCT4> </OCR_RVCT4>
<OCR_RVCT5> <OCR_RVCT5>
<Type>1</Type> <Type>1</Type>
...@@ -301,12 +301,12 @@ ...@@ -301,12 +301,12 @@
<OCR_RVCT9> <OCR_RVCT9>
<Type>0</Type> <Type>0</Type>
<StartAddress>0x20000000</StartAddress> <StartAddress>0x20000000</StartAddress>
<Size>0x10000</Size> <Size>0xff00</Size>
</OCR_RVCT9> </OCR_RVCT9>
<OCR_RVCT10> <OCR_RVCT10>
<Type>0</Type> <Type>0</Type>
<StartAddress>0x0</StartAddress> <StartAddress>0x2000ff00</StartAddress>
<Size>0x0</Size> <Size>0x100</Size>
</OCR_RVCT10> </OCR_RVCT10>
</OnChipMemories> </OnChipMemories>
<RvctStartVector></RvctStartVector> <RvctStartVector></RvctStartVector>
......
Firmware/Project/Cmsemicon/BAT32A279/MDK_ARM/RTE/Device/BAT32A239KK64FB/isr_BAT32A239.c deleted 100644 → 0
View file @ 6e32a063
/***********************************************************************************************************************
* Copyright (C) All rights reserved.
***********************************************************************************************************************/
/***********************************************************************************************************************
* @file isr.c
* @brief This file implements device driver for interrupt module.
* @version 1.0.0
* @date 2021/06/03
***********************************************************************************************************************/
/***********************************************************************************************************************
Includes
***********************************************************************************************************************/
#include "userdefine.h"
#include "BAT32A239.h"
/***********************************************************************************************************************
Pragma directive
***********************************************************************************************************************/
/***********************************************************************************************************************
Global variables and functions
***********************************************************************************************************************/
/***********************************************************IRQ00_Handler************************************************************/
__WEAK void lvi_interrupt(void)
{
INTC_ClearPendingIRQ(LVI_IRQn);
}
__WEAK void osdc_interrupt(void)
{
INTC_ClearPendingIRQ(OSDC_IRQn);
}
__WEAK void ocrv_interrupt(void)
{
INTC_ClearPendingIRQ(OCRV_IRQn);
}
//void IRQ00_Handler(void)
//{
// if(INTC_GetPendingIRQ(LVI_IRQn))
// {
// lvi_interrupt();
// }
//
// if(INTC_GetPendingIRQ(OSDC_IRQn))
// {
// osdc_interrupt();
// }
//
// if(INTC_GetPendingIRQ(OCRV_IRQn))
// {
// ocrv_interrupt();
// }
//}
///***********************************************************IRQ01_Handler************************************************************/
//__WEAK void intp0_interrupt(void)
//{
// INTC_ClearPendingIRQ(INTP0_IRQn);
//}
//__WEAK void intp6_interrupt(void)
//{
// INTC_ClearPendingIRQ(INTP6_IRQn);
//}
//void IRQ01_Handler(void)
//{
// if(INTC_GetPendingIRQ(INTP0_IRQn))
// {
// intp0_interrupt();
// }
//
// if(INTC_GetPendingIRQ(INTP6_IRQn))
// {
// intp6_interrupt();
// }
//
//}
///***********************************************************IRQ02_Handler************************************************************/
//__WEAK void intp1_interrupt(void)
//{
// INTC_ClearPendingIRQ(INTP1_IRQn);
//}
//__WEAK void intp7_interrupt(void)
//{
// INTC_ClearPendingIRQ(INTP7_IRQn);
//}
//void IRQ02_Handler(void)
//{
// if(INTC_GetPendingIRQ(INTP1_IRQn))
// {
// intp1_interrupt();
// }
//
// if(INTC_GetPendingIRQ(INTP7_IRQn))
// {
// intp7_interrupt();
// }
//
//}
///***********************************************************IRQ03_Handler************************************************************/
//__WEAK void intp2_interrupt(void)
//{
// INTC_ClearPendingIRQ(INTP2_IRQn);
//}
//__WEAK void intp8_interrupt(void)
//{
// INTC_ClearPendingIRQ(INTP8_IRQn);
//}
//void IRQ03_Handler(void)
//{
// if(INTC_GetPendingIRQ(INTP2_IRQn))
// {
// intp2_interrupt();
// }
//
// if(INTC_GetPendingIRQ(INTP8_IRQn))
// {
// intp8_interrupt();
// }
//
//}
///***********************************************************IRQ04_Handler************************************************************/
//__WEAK void intp3_interrupt(void)
//{
// INTC_ClearPendingIRQ(INTP3_IRQn);
//}
//__WEAK void intp9_interrupt(void)
//{
// INTC_ClearPendingIRQ(INTP9_IRQn);
//}
//void IRQ04_Handler(void)
//{
// if(INTC_GetPendingIRQ(INTP3_IRQn))
// {
// intp3_interrupt();
// }
//
// if(INTC_GetPendingIRQ(INTP9_IRQn))
// {
// intp9_interrupt();
// }
//
//}
///***********************************************************IRQ05_Handler************************************************************/
//__WEAK void intp4_interrupt(void)
//{
// INTC_ClearPendingIRQ(INTP4_IRQn);
//}
//__WEAK void intp10_interrupt(void)
//{
// INTC_ClearPendingIRQ(INTP10_IRQn);
//}
//void IRQ05_Handler(void)
//{
// if(INTC_GetPendingIRQ(INTP4_IRQn))
// {
// intp4_interrupt();
// }
//
// if(INTC_GetPendingIRQ(INTP10_IRQn))
// {
// intp10_interrupt();
// }
//
//}
///***********************************************************IRQ06_Handler************************************************************/
//__WEAK void intp5_interrupt(void)
//{
// INTC_ClearPendingIRQ(INTP5_IRQn);
//}
//__WEAK void intp11_interrupt(void)
//{
// INTC_ClearPendingIRQ(INTP11_IRQn);
//}
//void IRQ06_Handler(void)
//{
// if(INTC_GetPendingIRQ(INTP5_IRQn))
// {
// intp5_interrupt();
// }
//
// if(INTC_GetPendingIRQ(INTP11_IRQn))
// {
// intp11_interrupt();
// }
//
//}
///***********************************************************IRQ07_Handler************************************************************/
//__WEAK void uart2_interrupt_send(void)
//{
// INTC_ClearPendingIRQ(ST2_IRQn);
//}
//__WEAK void spi20_interrupt(void)
//{
// INTC_ClearPendingIRQ(SPI20_IRQn);
//}
//__WEAK void iic20_interrupt(void)
//{
// INTC_ClearPendingIRQ(IIC20_IRQn);
//}
//__WEAK void uart3_interrupt_send(void)
//{
// INTC_ClearPendingIRQ(ST3_IRQn);
//}
//__WEAK void spi30_interrupt(void)
//{
// INTC_ClearPendingIRQ(SPI30_IRQn);
//}
//__WEAK void iic30_interrupt(void)
//{
// INTC_ClearPendingIRQ(IIC30_IRQn);
//}
//void IRQ07_Handler(void)
//{
//#if defined(USE_SCI_UART2_TX)
// if(INTC_GetPendingIRQ(ST2_IRQn))
// {
// uart2_interrupt_send();
// }
//#elif defined(USE_SCI_SPI20)
// if(INTC_GetPendingIRQ(SPI20_IRQn))
// {
// spi20_interrupt();
// }
//#elif defined(USE_SCI_IIC20)
// if(INTC_GetPendingIRQ(IIC20_IRQn))
// {
// iic20_interrupt();
// }
//#endif
//#if defined(USE_SCI_UART3_TX)
// if(INTC_GetPendingIRQ(ST3_IRQn))
// {
// uart3_interrupt_send();
// }
//#elif defined(USE_SCI_SPI30)
// if(INTC_GetPendingIRQ(SPI30_IRQn))
// {
// spi30_interrupt();
// }
//#elif defined(USE_SCI_IIC30)
// if(INTC_GetPendingIRQ(IIC30_IRQn))
// {
// iic30_interrupt();
// }
//#endif
//}
///***********************************************************IRQ08_Handler************************************************************/
//__WEAK void uart2_interrupt_receive(void)
//{
// INTC_ClearPendingIRQ(SR2_IRQn);
//}
//__WEAK void spi21_interrupt(void)
//{
// INTC_ClearPendingIRQ(SPI21_IRQn);
//}
//__WEAK void iic21_interrupt(void)
//{
// INTC_ClearPendingIRQ(IIC21_IRQn);
//}
//__WEAK void uart3_interrupt_receive(void)
//{
// INTC_ClearPendingIRQ(SR3_IRQn);
//}
//__WEAK void spi31_interrupt(void)
//{
// INTC_ClearPendingIRQ(SPI31_IRQn);
//}
//__WEAK void iic31_interrupt(void)
//{
// INTC_ClearPendingIRQ(IIC31_IRQn);
//}
//void IRQ08_Handler(void)
//{
//#if defined(USE_SCI_UART2_RX)
// if(INTC_GetPendingIRQ(SR2_IRQn))
// {
// uart2_interrupt_receive();
// }
//#elif defined(USE_SCI_SPI21)
// if(INTC_GetPendingIRQ(SPI21_IRQn))
// {
// spi21_interrupt();
// }
//#elif defined(USE_SCI_IIC21)
// if(INTC_GetPendingIRQ(IIC21_IRQn))
// {
// iic21_interrupt();
// }
//#endif
//#if defined(USE_SCI_UART3_RX)
// if(INTC_GetPendingIRQ(SR3_IRQn))
// {
// uart3_interrupt_receive();
// }
//#elif defined(USE_SCI_SPI31)
// if(INTC_GetPendingIRQ(SPI31_IRQn))
// {
// spi31_interrupt();
// }
//#elif defined(USE_SCI_IIC31)
// if(INTC_GetPendingIRQ(IIC31_IRQn))
// {
// iic31_interrupt();
// }
//#endif
//}
///***********************************************************IRQ09_Handler************************************************************/
//__WEAK void sre2_interrupt(void)
//{
// INTC_ClearPendingIRQ(SRE2_IRQn);
//}
//__WEAK void CAN0Err_Interrupt(void)
//{
// INTC_ClearPendingIRQ(CAN0ERR_IRQn);
//}
//void IRQ09_Handler(void)
//{
// if(INTC_GetPendingIRQ(SRE2_IRQn))
// {
// sre2_interrupt();
// }
//
// if(INTC_GetPendingIRQ(CAN0ERR_IRQn))
// {
// CAN0Err_Interrupt();
// }
//
//}
///***********************************************************IRQ10_Handler************************************************************/
//__WEAK void uart0_interrupt_send(void)
//{
// INTC_ClearPendingIRQ(ST0_IRQn);
//}
//__WEAK void spi00_interrupt(void)
//{
// INTC_ClearPendingIRQ(SPI00_IRQn);
//}
//__WEAK void iic00_interrupt(void)
//{
// INTC_ClearPendingIRQ(IIC00_IRQn);
//}
//void IRQ10_Handler(void)
//{
//#if defined(USE_SCI_UART0_TX)
// if(INTC_GetPendingIRQ(ST0_IRQn))
// {
// uart0_interrupt_send();
// }
//#elif defined(USE_SCI_SPI00)
// if(INTC_GetPendingIRQ(SPI00_IRQn))
// {
// spi00_interrupt();
// }
//#elif defined(USE_SCI_IIC00)
// if(INTC_GetPendingIRQ(IIC00_IRQn))
// {
// iic00_interrupt();
// }
//#endif
//}
///***********************************************************IRQ11_Handler************************************************************/
//__WEAK void uart0_interrupt_receive(void)
//{
// INTC_ClearPendingIRQ(SR0_IRQn);
//}
//__WEAK void spi01_interrupt(void)
//{
// INTC_ClearPendingIRQ(SPI01_IRQn);
//}
//__WEAK void iic01_interrupt(void)
//{
// INTC_ClearPendingIRQ(IIC01_IRQn);
//}
//void IRQ11_Handler(void)
//{
//#if defined(USE_SCI_UART0_RX)
// if(INTC_GetPendingIRQ(SR0_IRQn))
// {
// uart0_interrupt_receive();
// }
//#elif defined(USE_SCI_SPI01)
// if(INTC_GetPendingIRQ(SPI01_IRQn))
// {
// spi01_interrupt();
// }
//#elif defined(USE_SCI_IIC01)
// if(INTC_GetPendingIRQ(IIC01_IRQn))
// {
// iic01_interrupt();
// }
//#endif
//}
///***********************************************************IRQ12_Handler************************************************************/
//__WEAK void sre0_interrupt(void)
//{
// INTC_ClearPendingIRQ(SRE0_IRQn);
//}
//__WEAK void tm01h_interrupt(void)
//{
// INTC_ClearPendingIRQ(TM01H_IRQn);
//}
//void IRQ12_Handler(void)
//{
// if(INTC_GetPendingIRQ(SRE0_IRQn))
// {
// sre0_interrupt();
// }
//
// if(INTC_GetPendingIRQ(TM01H_IRQn))
// {
// tm01h_interrupt();
// }
//
//}
///***********************************************************IRQ13_Handler************************************************************/
//__WEAK void uart1_interrupt_send(void)
//{
// INTC_ClearPendingIRQ(ST1_IRQn);
//}
//__WEAK void spi10_interrupt(void)
//{
// INTC_ClearPendingIRQ(SPI10_IRQn);
//}
//__WEAK void iic10_interrupt(void)
//{
// INTC_ClearPendingIRQ(IIC10_IRQn);
//}
//void IRQ13_Handler(void)
//{
//#if defined(USE_SCI_UART1_TX)
// if(INTC_GetPendingIRQ(ST1_IRQn))
// {
// uart1_interrupt_send();
// }
//#elif defined(USE_SCI_SPI10)
// if(INTC_GetPendingIRQ(SPI10_IRQn))
// {
// spi10_interrupt();
// }
//#elif defined(USE_SCI_IIC10)
// if(INTC_GetPendingIRQ(IIC10_IRQn))
// {
// iic10_interrupt();
// }
//#endif
//}
///***********************************************************IRQ14_Handler************************************************************/
//__WEAK void uart1_interrupt_receive(void)
//{
// INTC_ClearPendingIRQ(SR1_IRQn);
//}
//__WEAK void spi11_interrupt(void)
//{
// INTC_ClearPendingIRQ(SPI11_IRQn);
//}
//__WEAK void iic11_interrupt(void)
//{
// INTC_ClearPendingIRQ(IIC11_IRQn);
//}
//void IRQ14_Handler(void)
//{
//#if defined(USE_SCI_UART1_RX)
// if(INTC_GetPendingIRQ(SR1_IRQn))
// {
// uart1_interrupt_receive();
// }
//#elif defined(USE_SCI_SPI11)
// if(INTC_GetPendingIRQ(SPI11_IRQn))
// {
// spi11_interrupt();
// }
//#elif defined(USE_SCI_IIC11)
// if(INTC_GetPendingIRQ(IIC11_IRQn))
// {
// iic11_interrupt();
// }
//#endif
//}
///***********************************************************IRQ15_Handler************************************************************/
//__WEAK void sre1_interrupt(void)
//{
// INTC_ClearPendingIRQ(SRE1_IRQn);
//}
//__WEAK void tm03h_interrupt(void)
//{
// INTC_ClearPendingIRQ(TM03H_IRQn);
//}
//void IRQ15_Handler(void)
//{
// if(INTC_GetPendingIRQ(SRE1_IRQn))
// {
// sre1_interrupt();
// }
//
// if(INTC_GetPendingIRQ(TM03H_IRQn))
// {
// tm03h_interrupt();
// }
//
//}
///***********************************************************IRQ16_Handler************************************************************/
//__WEAK void iica0_interrupt(void)
//{
// INTC_ClearPendingIRQ(IICA0_IRQn);
//}
//__WEAK void div_interrupt(void)
//{
// INTC_ClearPendingIRQ(DIV_IRQn);
//}
//__WEAK void iica1_interrupt(void)
//{
// INTC_ClearPendingIRQ(IICA1_IRQn);
//}
//void IRQ16_Handler(void)
//{
// if(INTC_GetPendingIRQ(IICA0_IRQn))
// {
// iica0_interrupt();
// }
//
// if(INTC_GetPendingIRQ(DIV_IRQn))
// {
// div_interrupt();
// }
//
// if(INTC_GetPendingIRQ(IICA1_IRQn))
// {
// iica1_interrupt();
// }
//
//}
///***********************************************************IRQ17_Handler************************************************************/
//__WEAK void tm40_channel0_interrupt(void)
//{
// INTC_ClearPendingIRQ(TM00_IRQn);
//}
//__WEAK void tm81_channel10_interrupt(void)
//{
// INTC_ClearPendingIRQ(TM10_IRQn);
//}
//__WEAK void tm81_channel14_interrupt(void)
//{
// INTC_ClearPendingIRQ(TM14_IRQn);
//}
//void IRQ17_Handler(void)
//{
// if(INTC_GetPendingIRQ(TM00_IRQn))
// {
// tm40_channel0_interrupt();
// }
//
// if(INTC_GetPendingIRQ(TM10_IRQn))
// {
// tm81_channel10_interrupt();
// }
//
// if(INTC_GetPendingIRQ(TM14_IRQn))
// {
// tm81_channel14_interrupt();
// }
//}
///***********************************************************IRQ18_Handler************************************************************/
//__WEAK void tm40_channel1_interrupt(void)
//{
// INTC_ClearPendingIRQ(TM01_IRQn);
//}
//__WEAK void tm81_channel11_interrupt(void)
//{
// INTC_ClearPendingIRQ(TM11_IRQn);
//}
//__WEAK void tm81_channel15_interrupt(void)
//{
// INTC_ClearPendingIRQ(TM15_IRQn);
//}
//void IRQ18_Handler(void)
//{
// if(INTC_GetPendingIRQ(TM01_IRQn))
// {
// tm40_channel1_interrupt();
// }
//
// if(INTC_GetPendingIRQ(TM11_IRQn))
// {
// tm81_channel11_interrupt();
// }
//
// if(INTC_GetPendingIRQ(TM15_IRQn))
// {
// tm81_channel15_interrupt();
// }
//}
///***********************************************************IRQ19_Handler************************************************************/
//__WEAK void tm40_channel2_interrupt(void)
//{
// INTC_ClearPendingIRQ(TM02_IRQn);
//}
//__WEAK void tm81_channel12_interrupt(void)
//{
// INTC_ClearPendingIRQ(TM12_IRQn);
//}
//__WEAK void tm81_channel16_interrupt(void)
//{
// INTC_ClearPendingIRQ(TM16_IRQn);
//}
//void IRQ19_Handler(void)
//{
// if(INTC_GetPendingIRQ(TM02_IRQn))
// {
// tm40_channel2_interrupt();
// }
//
// if(INTC_GetPendingIRQ(TM12_IRQn))
// {
// tm81_channel12_interrupt();
// }
//
// if(INTC_GetPendingIRQ(TM16_IRQn))
// {
// tm81_channel16_interrupt();
// }
//}
///***********************************************************IRQ20_Handler************************************************************/
//__WEAK void tm40_channel3_interrupt(void)
//{
// INTC_ClearPendingIRQ(TM03_IRQn);
//}
//__WEAK void tm81_channel13_interrupt(void)
//{
// INTC_ClearPendingIRQ(TM13_IRQn);
//}
//__WEAK void tm81_channel17_interrupt(void)
//{
// INTC_ClearPendingIRQ(TM17_IRQn);
//}
//void IRQ20_Handler(void)
//{
// if(INTC_GetPendingIRQ(TM03_IRQn))
// {
// tm40_channel3_interrupt();
// }
//
// if(INTC_GetPendingIRQ(TM13_IRQn))
// {
// tm81_channel13_interrupt();
// }
//
// if(INTC_GetPendingIRQ(TM17_IRQn))
// {
// tm81_channel17_interrupt();
// }
//}
///***********************************************************IRQ21_Handler************************************************************/
//__WEAK void adc_interrupt(void)
//{
// INTC_ClearPendingIRQ(ADC_IRQn);
//}
//void IRQ21_Handler(void)
//{
// if(INTC_GetPendingIRQ(ADC_IRQn))
// {
// adc_interrupt();
// }
//
//}
///***********************************************************IRQ22_Handler************************************************************/
//__WEAK void rtc_interrupt(void)
//{
// INTC_ClearPendingIRQ(RTC_IRQn);
//}
//__WEAK void it_interrupt(void)
//{
// INTC_ClearPendingIRQ(IT_IRQn);
//}
//void IRQ22_Handler(void)
//{
// if(INTC_GetPendingIRQ(RTC_IRQn))
// {
// rtc_interrupt();
// }
//
// if(INTC_GetPendingIRQ(IT_IRQn))
// {
// it_interrupt();
// }
//
//}
///***********************************************************IRQ23_Handler************************************************************/
//__WEAK void key_interrupt(void)
//{
// INTC_ClearPendingIRQ(KEY_IRQn);
//}
//__WEAK void CAN0Rec_Interrupt(void)
//{
// INTC_ClearPendingIRQ(CAN0REC_IRQn);
//}
//void IRQ23_Handler(void)
//{
// if(INTC_GetPendingIRQ(KEY_IRQn))
// {
// key_interrupt();
// }
//
// if(INTC_GetPendingIRQ(CAN0REC_IRQn))
// {
// CAN0Rec_Interrupt();
// }
//
//}
///***********************************************************IRQ24_Handler************************************************************/
//__WEAK void cmp0_interrupt(void)
//{
// INTC_ClearPendingIRQ(CMP0_IRQn);
//}
//__WEAK void CAN0Wup_Interrupt(void)
//{
// INTC_ClearPendingIRQ(CAN0WUP_IRQn);
//}
//void IRQ24_Handler(void)
//{
// if(INTC_GetPendingIRQ(CMP0_IRQn))
// {
// cmp0_interrupt();
// }
//
// if(INTC_GetPendingIRQ(CAN0WUP_IRQn))
// {
// CAN0Wup_Interrupt();
// }
//
//}
///***********************************************************IRQ25_Handler************************************************************/
//__WEAK void cmp1_interrupt(void)
//{
// INTC_ClearPendingIRQ(CMP1_IRQn);
//}
//__WEAK void CAN0Trx_Interrupt(void)
//{
// INTC_ClearPendingIRQ(CAN0TRX_IRQn);
//}
//void IRQ25_Handler(void)
//{
// if(INTC_GetPendingIRQ(CMP1_IRQn))
// {
// cmp1_interrupt();
// }
//
// if(INTC_GetPendingIRQ(CAN0TRX_IRQn))
// {
// CAN0Trx_Interrupt();
// }
//
//}
///***********************************************************IRQ26_Handler************************************************************/
//__WEAK void tma0_interrupt(void)
//{
// INTC_ClearPendingIRQ(TMA_IRQn);
//}
//__WEAK void CAN1Err_Interrupt(void)
//{
// INTC_ClearPendingIRQ(CAN1ERR_IRQn);
//}
//void IRQ26_Handler(void)
//{
// if(INTC_GetPendingIRQ(TMA_IRQn))
// {
// tma0_interrupt();
// }
//
// if(INTC_GetPendingIRQ(CAN1ERR_IRQn))
// {
// CAN1Err_Interrupt();
// }
//
//}
///***********************************************************IRQ27_Handler************************************************************/
//__WEAK void tmm0_interrupt(void)
//{
// INTC_ClearPendingIRQ(TMM0_IRQn);
//}
//void IRQ27_Handler(void)
//{
// if(INTC_GetPendingIRQ(TMM0_IRQn))
// {
// tmm0_interrupt();
// }
//
//}
///***********************************************************IRQ28_Handler************************************************************/
//__WEAK void tmm1_interrupt(void)
//{
// INTC_ClearPendingIRQ(TMM1_IRQn);
//}
//void IRQ28_Handler(void)
//{
// if(INTC_GetPendingIRQ(TMM1_IRQn))
// {
// tmm1_interrupt();
// }
//
//}
///***********************************************************IRQ29_Handler************************************************************/
//__WEAK void tmb0_interrupt(void)
//{
// INTC_ClearPendingIRQ(TMB_IRQn);
//}
//__WEAK void CAN1Rec_Interrupt(void)
//{
// INTC_ClearPendingIRQ(CAN1REC_IRQn);
//}
//void IRQ29_Handler(void)
//{
// if(INTC_GetPendingIRQ(TMB_IRQn))
// {
// tmb0_interrupt();
// }
//
// if(INTC_GetPendingIRQ(CAN1REC_IRQn))
// {
// CAN1Rec_Interrupt();
// }
//
//}
///***********************************************************IRQ30_Handler************************************************************/
//__WEAK void tmc_interrupt(void)
//{
// INTC_ClearPendingIRQ(TMC_IRQn);
//}
//__WEAK void CAN1Wup_Interrupt(void)
//{
// INTC_ClearPendingIRQ(CAN1WUP_IRQn);
//}
//void IRQ30_Handler(void)
//{
// if(INTC_GetPendingIRQ(TMC_IRQn))
// {
// tmc_interrupt();
// }
//
// if(INTC_GetPendingIRQ(CAN1WUP_IRQn))
// {
// CAN1Wup_Interrupt();
// }
//
//}
///***********************************************************IRQ31_Handler************************************************************/
//__WEAK void flash_interrupt(void)
//{
// INTC_ClearPendingIRQ(FMC_IRQn);
//}
//__WEAK void CAN1Trx_Interrupt(void)
//{
// INTC_ClearPendingIRQ(CAN1TRX_IRQn);
//}
//void IRQ31_Handler(void)
//{
// if(INTC_GetPendingIRQ(FMC_IRQn))
// {
// flash_interrupt();
// }
//
// if(INTC_GetPendingIRQ(CAN1TRX_IRQn))
// {
// CAN1Trx_Interrupt();
// }
//
//}
Firmware/Project/Cmsemicon/BAT32A279/MDK_ARM/RTE/Device/BAT32A239KK64FB/startup_BAT32A239.s deleted 100644 → 0
View file @ 6e32a063
;/**************************************************************************//**
; * @file startup_BAT32A239.s
; * @brief CMSIS Cortex-M ARMv6-M based Core Device Startup File for
; * Device BAT32A239
; * @version V1.00
; * @date 2019/04/24
; ******************************************************************************/
;/*
; * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
; *
; * SPDX-License-Identifier: Apache-2.0
; *
; * Licensed under the Apache License, Version 2.0 (the License); you may
; * not use this file except in compliance with the License.
; * You may obtain a copy of the License at
; *
; * www.apache.org/licenses/LICENSE-2.0
; *
; * Unless required by applicable law or agreed to in writing, software
; * distributed under the License is distributed on an AS IS BASIS, WITHOUT
; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
; * See the License for the specific language governing permissions and
; * limitations under the License.
; */
;/*
;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
;*/
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Stack_Size EQU 0x00000600
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Heap_Size EQU 0x00000100
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
; ToDo: Add here the vectors for the device specific external interrupts handler
DCD IRQ00_Handler ; LVI IRQ
DCD IRQ01_Handler ; INTP0 or INTP6 IRQ
DCD IRQ02_Handler ; INTP1 or INTP7 IRQ
DCD IRQ03_Handler ; INTP2 or INTP8 IRQ
DCD IRQ04_Handler ; INTP3 or INTP9 IRQ
DCD IRQ05_Handler ; INTP4 or INTP10 IRQ
DCD IRQ06_Handler ; INTP5 or INTP11 IRQ
DCD IRQ07_Handler ; ST2/SPI20/IIC20 IRQ
DCD IRQ08_Handler ; SR2/SPI21/IIC21 IRQ
DCD IRQ09_Handler ; SRE2 IRQ
DCD IRQ10_Handler ; ST0/SPI00/IIC00 IRQ
DCD IRQ11_Handler ; SR0/SPI01/IIC01 IRQ
DCD IRQ12_Handler ; SRE0 or TM01H IRQ
DCD IRQ13_Handler ; ST1/SPI10/IIC10 IRQ
DCD IRQ14_Handler ; SR1/SPI11/IIC11 IRQ
DCD IRQ15_Handler ; SRE1 or TM03H IRQ
DCD IRQ16_Handler ; IICA or DIV IRQ
DCD IRQ17_Handler ; TM00 IRQ
DCD IRQ18_Handler ; TM01 IRQ
DCD IRQ19_Handler ; TM02 IRQ
DCD IRQ20_Handler ; TM03 IRQ
DCD IRQ21_Handler ; ADC IRQ
DCD IRQ22_Handler ; RTC or IT IRQ
DCD IRQ23_Handler ; KEY IRQ
DCD IRQ24_Handler ; CMP0 IRQ
DCD IRQ25_Handler ; CMP1 IRQ
DCD IRQ26_Handler ; TMA IRQ
DCD IRQ27_Handler ; TMM0 IRQ
DCD IRQ28_Handler ; TMM1 IRQ
DCD IRQ29_Handler ; TMB IRQ
DCD IRQ30_Handler ; TMC IRQ
DCD IRQ31_Handler ; FMC IRQ
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset Handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT SystemInit
IMPORT __main
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler\
PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
MemManage_Handler\
PROC
EXPORT MemManage_Handler [WEAK]
B .
ENDP
BusFault_Handler\
PROC
EXPORT BusFault_Handler [WEAK]
B .
ENDP
UsageFault_Handler\
PROC
EXPORT UsageFault_Handler [WEAK]
B .
ENDP
SVC_Handler\
PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
DebugMon_Handler\
PROC
EXPORT DebugMon_Handler [WEAK]
B .
ENDP
PendSV_Handler\
PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler\
PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
IRQ00_Handler\
PROC
EXPORT IRQ00_Handler [WEAK]
B .
ENDP
IRQ01_Handler\
PROC
EXPORT IRQ01_Handler [WEAK]
B .
ENDP
IRQ02_Handler\
PROC
EXPORT IRQ02_Handler [WEAK]
B .
ENDP
IRQ03_Handler\
PROC
EXPORT IRQ03_Handler [WEAK]
B .
ENDP
IRQ04_Handler\
PROC
EXPORT IRQ04_Handler [WEAK]
B .
ENDP
IRQ05_Handler\
PROC
EXPORT IRQ05_Handler [WEAK]
B .
ENDP
IRQ06_Handler\
PROC
EXPORT IRQ06_Handler [WEAK]
B .
ENDP
IRQ07_Handler\
PROC
EXPORT IRQ07_Handler [WEAK]
B .
ENDP
IRQ08_Handler\
PROC
EXPORT IRQ08_Handler [WEAK]
B .
ENDP
IRQ09_Handler\
PROC
EXPORT IRQ09_Handler [WEAK]
B .
ENDP
IRQ10_Handler\
PROC
EXPORT IRQ10_Handler [WEAK]
B .
ENDP
IRQ11_Handler\
PROC
EXPORT IRQ11_Handler [WEAK]
B .
ENDP
IRQ12_Handler\
PROC
EXPORT IRQ12_Handler [WEAK]
B .
ENDP
IRQ13_Handler\
PROC
EXPORT IRQ13_Handler [WEAK]
B .
ENDP
IRQ14_Handler\
PROC
EXPORT IRQ14_Handler [WEAK]
B .
ENDP
IRQ15_Handler\
PROC
EXPORT IRQ15_Handler [WEAK]
B .
ENDP
IRQ16_Handler\
PROC
EXPORT IRQ16_Handler [WEAK]
B .
ENDP
IRQ17_Handler\
PROC
EXPORT IRQ17_Handler [WEAK]
B .
ENDP
IRQ18_Handler\
PROC
EXPORT IRQ18_Handler [WEAK]
B .
ENDP
IRQ19_Handler\
PROC
EXPORT IRQ19_Handler [WEAK]
B .
ENDP
IRQ20_Handler\
PROC
EXPORT IRQ20_Handler [WEAK]
B .
ENDP
IRQ21_Handler\
PROC
EXPORT IRQ21_Handler [WEAK]
B .
ENDP
IRQ22_Handler\
PROC
EXPORT IRQ22_Handler [WEAK]
B .
ENDP
IRQ23_Handler\
PROC
EXPORT IRQ23_Handler [WEAK]
B .
ENDP
IRQ24_Handler\
PROC
EXPORT IRQ24_Handler [WEAK]
B .
ENDP
IRQ25_Handler\
PROC
EXPORT IRQ25_Handler [WEAK]
B .
ENDP
IRQ26_Handler\
PROC
EXPORT IRQ26_Handler [WEAK]
B .
ENDP
IRQ27_Handler\
PROC
EXPORT IRQ27_Handler [WEAK]
B .
ENDP
IRQ28_Handler\
PROC
EXPORT IRQ28_Handler [WEAK]
B .
ENDP
IRQ29_Handler\
PROC
EXPORT IRQ29_Handler [WEAK]
B .
ENDP
IRQ30_Handler\
PROC
EXPORT IRQ30_Handler [WEAK]
B .
ENDP
IRQ31_Handler\
PROC
EXPORT IRQ31_Handler [WEAK]
B .
ENDP
ALIGN
; User Initial Stack & Heap
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap PROC
LDR R0, = Heap_Mem
LDR R1, =(Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ENDP
ALIGN
ENDIF
END
Firmware/Project/Cmsemicon/BAT32A279/MDK_ARM/RTE/Device/BAT32A239KK64FB/system_BAT32A239.c deleted 100644 → 0
View file @ 6e32a063
/**************************************************************************//**
* @file system_BAT32A239.c
* @brief CMSIS Cortex-M0+ Device Peripheral Access Layer Source File for
* Device BAT32A239
* @version V1.00
* @date 2019/04/24
******************************************************************************/
/*
* Copyright (c) 2009-2018 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include <stdint.h>
#include "BAT32A239.h"
#include "userdefine.h"
/*----------------------------------------------------------------------------
Define clocks
*----------------------------------------------------------------------------*/
/* ToDo: add here your necessary defines for device initialization
following is an example for different system frequencies */
#define __HSI (64000000UL)
#define __XTAL (8000000UL) /* Oscillator frequency */
#define __SYS_OSC_CLK (___HSI) /* Main oscillator frequency */
#define __SYSTEM_CLOCK (64000000UL)
/** @addtogroup Configuration_of_User_Option_Byte
* @{
*/
typedef enum {
HOCO_FREQ_64MHZ = 0xF8, /*!< fHOCO = 64MHz, fIH = 64MHz */
HOCO_FREQ_48MHZ = 0xF0, /*!< fHOCO = 48MHz, fIH = 48MHz */
HOCO_FREQ_32MHZ = 0xE8, /*!< fHOCO = 32MHz, fIH = 32MHz */
HOCO_FREQ_24MHZ = 0xE0, /*!< fHOCO = 24MHz, fIH = 24MHz */
HOCO_FREQ_16MHZ = 0xE9, /*!< fHOCO = 32MHz, fIH = 16MHz */
HOCO_FREQ_12MHZ = 0xE1, /*!< fHOCO = 24MHz, fIH = 12MHz */
HOCO_FREQ_8MHZ = 0xEA, /*!< fHOCO = 32MHz, fIH = 8MHz */
HOCO_FREQ_6MHZ = 0xE2, /*!< fHOCO = 24MHz, fIH = 6MHz */
HOCO_FREQ_4MHZ = 0xEB, /*!< fHOCO = 32MHz, fIH = 4MHz */
HOCO_FREQ_3MHZ = 0xE3, /*!< fHOCO = 24MHz, fIH = 3MHz */
HOCO_FREQ_2MHZ = 0xEC, /*!< fHOCO = 32MHz, fIH = 2MHz */
HOCO_FREQ_1MHZ = 0xED /*!< fHOCO = 32MHz, fIH = 1MHz */
} hoco_freq_t;
/*----------------------------------------------------------------------------
User Option Byte
*----------------------------------------------------------------------------*/
/* ToDo: add here your necessary defines for device initialization
following is an example for different system frequencies */
//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
#if HAS_BOOTLOADER
const uint8_t user_opt_data[4] __attribute__((used)) __attribute__((section(".ARM.__AT_0x000080C0"))) =
#else
const uint8_t user_opt_data[4] __attribute__((used)) __attribute__((section(".ARM.__AT_0x000000C0"))) =
#endif
{
/**
* @brief WDT Control BYTE
* Please refer to the user manual for details.
* 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
* --------|---------|---------|-------|-------|-------|-------|----------
* WDTINT | WINDOW1 | WINDOW0 | WDTON | WDCS2 | WDCS1 | WDCS0 | WDSTBYON
* --------|---------|---------|-------|-------|-------|-------|----------
*/
// <h> WDT Control Option Byte (C0H)
// <e.4> Enable WDT (WDTON)
// <o.5..6> Watchdog timer window open period setting <2=> 75% <3=> 100%
// <o.1..3> Watchdog timer overflow time setting <0=> 2^6/fIL <1=> 2^7/fIL
// <2=> 2^8/fIL <3=> 2^9/fIL
// <4=> 2^11/fIL <5=> 2^13/fIL
// <6=> 2^14/fIL <7=> 2^16/fIL
// <e.0> Operation in Standby mode setting (WDSTBYON)
// <i> WDT Operaton in SLEEP/DEEPSLEEP mode.
// </e>
// <e.7> interrupt enable
// <i> interval interrupt is generated when 75% + 1/2 fIL of the overflow time is reached.
// </e>
// </e>
// </h>
0x7C, //0xEF WDT-OFF 0x7F WDT-ON
/**
* @brief LVD Control BYTE (C1H)
* Please refer to the user manual for details.
* 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
* -------|-------|-------|-------|-------|-------|---------|----------
* VPOC2 | VPOC1 | VPOC0 | 1 | LVIS1 | LVIS0 | LVIMDS1 | LVIMDS0
* -------|-------|-------|-------|-------|-------|---------|----------
*/
// <h> LVD Control Option Byte (C1H)
// <o.0..7> Voltage detection setting (VLVD) <0xFF=> ( LVD OFF )
// <0x39=> VLVD = 1.98V/1.94V ( interrupt mode )
// <0x35=> VLVD = 2.09V/2.04V ( interrupt mode )
// <0x5D=> VLVD = 2.50V/2.45V ( interrupt mode )
// <0x59=> VLVD = 2.61V/2.55V ( interrupt mode )
// <0x55=> VLVD = 2.71V/2.65V ( interrupt mode )
// <0x7D=> VLVD = 2.81V/2.75V ( interrupt mode )
// <0x79=> VLVD = 2.92V/2.86V ( interrupt mode )
// <0x75=> VLVD = 3.02V/2.96V ( interrupt mode )
// <0x3B=> VLVD = 1.98V/1.94V ( reset mode )
// <0x37=> VLVD = 2.09V/2.04V ( reset mode )
// <0x5F=> VLVD = 2.50V/2.45V ( reset mode )
// <0x5B=> VLVD = 2.61V/2.55V ( reset mode )
// <0x57=> VLVD = 2.71V/2.65V ( reset mode )
// <0x7F=> VLVD = 2.81V/2.75V ( reset mode )
// <0x7B=> VLVD = 2.92V/2.86V ( reset mode )
// <0x77=> VLVD = 3.02V/2.96V ( reset mode )
// <0x36=> VLVDH = 2.09V/2.04V, VLVDL = 1.84V ( interrupt & reset mode )
// <0x32=> VLVDH = 3.13V/3.06V, VLVDL = 1.84V ( interrupt & reset mode )
// <0x5A=> VLVDH = 2.61V/2.55V, VLVDL = 2.45V ( interrupt & reset mode )
// <0x56=> VLVDH = 2.71V/2.65V, VLVDL = 2.45V ( interrupt & reset mode )
// <0x52=> VLVDH = 3.75V/3.67V, VLVDL = 2.45V ( interrupt & reset mode )
// <0x7A=> VLVDH = 2.92V/2.86V, VLVDL = 2.75V ( interrupt & reset mode )
// <0x76=> VLVDH = 3.02V/2.96V, VLVDL = 2.75V ( interrupt & reset mode )
// <0x72=> VLVDH = 4.06V/3.98V, VLVDL = 2.75V ( interrupt & reset mode )
// <i> Please setting the item for interrupt & reset mode
// </h>
0x3B,
/**
* @brief HOCO Control BYTE (FRQSEL)
* Please refer to the user manual for details.
* 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
* -------|-------|-------|---------|---------|---------|---------|---------
* 1 | 1 | 1 | FRQSEL4 | FRQSEL3 | FRQSEL2 | FRQSEL1 | FRQSEL0
* -------|-------|-------|---------|---------|---------|---------|---------
*/
// <h> HOCO Control Option Byte (C2H)
// <o.0..4> High-speed OCO clock setting <0xF8=> fHOCO = 64MHz, fIH = 64MHz
// <0xF0=> fHOCO = 48MHz, fIH = 48MHz
// <0xE8=> fHOCO = 32MHz, fIH = 32MHz
// <0xE0=> fHOCO = 24MHz, fIH = 24MHz
// <0xE9=> fHOCO = 32MHz, fIH = 16MHz
// <0xE1=> fHOCO = 24MHz, fIH = 12MHz
// <0xEA=> fHOCO = 32MHz, fIH = 8MHz
// <0xE2=> fHOCO = 24MHz, fIH = 6MHz
// <0xEB=> fHOCO = 32MHz, fIH = 4MHz
// <0xE3=> fHOCO = 24MHz, fIH = 3MHz
// <0xEC=> fHOCO = 32MHz, fIH = 2MHz
// <0xED=> fHOCO = 32MHz, fIH = 1MHz
// </h>
0xF8,
/**
* @brief Flash Protect Control BYTE
* Please refer to the user manual for details.
*/
// <h> OCD Control Option Byte (C3H)
// <o.0..7> On-chip debug setting (OCDEN) <0xFF=> Enable <0xC3=> Disable
// <i> OCDM(500004H) == 0x3C && OCDEN == 0xC3: Debugger can not erease/write/read Flash.
// <i> OCDM(500004H) != 0x3C && OCDEN == 0xC3: Debugger can only chip erease Flash but cannot write/read Flash.
// </h>
0xFF
};
//-------- <<< end of configuration section >>> ------------------
/** @} */ /* End of group Configuration_of_User_Option_Byte */
/*----------------------------------------------------------------------------
System Core Clock Variable
*----------------------------------------------------------------------------*/
/* ToDo: initialize SystemCoreClock with the system core clock frequency value
achieved after system intitialization.
This means system core clock frequency after call to SystemInit() */
uint32_t SystemCoreClock; /* System Clock Frequency (Core Clock)*/
/*----------------------------------------------------------------------------
Clock functions
*----------------------------------------------------------------------------*/
__WEAK uint32_t CLK_GetfIHFreq(void)
{
uint32_t freq;
uint8_t frqsel = (*(uint8_t *)0x000000C2U);
frqsel &= 0xF8; /* Mask the lower 3 bits */
frqsel |= CGC->HOCODIV; /* Refer the value of HOCODIV */
switch(frqsel)
{
case HOCO_FREQ_64MHZ:
freq = 64000000U; /* fIH = 64MHz */
break;
case HOCO_FREQ_48MHZ:
freq = 48000000U; /* fIH = 48MHz */
break;
case HOCO_FREQ_32MHZ:
freq = 32000000U; /* fIH = 32MHz */
break;
case HOCO_FREQ_24MHZ:
freq = 24000000U; /* fIH = 24MHz */
break;
case HOCO_FREQ_16MHZ:
freq = 16000000U; /* fIH = 16MHz */
break;
case HOCO_FREQ_12MHZ:
freq = 12000000U; /* fIH = 12MHz */
break;
case HOCO_FREQ_8MHZ:
freq = 8000000U; /* fIH = 8MHz */
break;
case HOCO_FREQ_6MHZ:
freq = 6000000U; /* fIH = 6MHz */
break;
case HOCO_FREQ_4MHZ:
freq = 4000000U; /* fIH = 4MHz */
break;
case HOCO_FREQ_3MHZ:
freq = 3000000U; /* fIH = 3MHz */
break;
case HOCO_FREQ_2MHZ:
freq = 2000000U; /* fIH = 2MHz */
break;
case HOCO_FREQ_1MHZ:
freq = 1000000U; /* fIH = 1MHz */
break;
default:
freq = 1000000U; /* fIH = 1MHz */
break;
}
return(freq);
}
__WEAK uint32_t CLK_GetCoreFreq(void)
{
uint32_t freq;
uint8_t pllsel = 0;
if(CGC->CKC&0x20){ // Main Osc
freq = __XTAL; /* Get XTAL frequency */
}
else{ // fIH
freq = CLK_GetfIHFreq(); /* Get fIH frequency */
if(CGC->MCKC&0x80){ /* CGC->MCKC&0x80 = 0x80: PLL On */
if (CGC->PLLCR&0x80){ // XTAL + PLL
freq = __XTAL; /* Get XTAL frequency */
}
else{ // fIH + PLL
freq = CLK_GetfIHFreq(); /* Get fIH frequency */
}
pllsel = (CGC->PLLCR >> 2)&0x03; // PLL div in PLLCR
if(pllsel>=2){ // PLL Div=4
freq = freq/4;
}
else if(pllsel==1){ // PLL Div=2
freq = freq/2;
}
else{ // PLL Div=1
freq = freq/1;
}
if((CGC->PLLCR >> 1)&0x01){ // PLL Mul in PLLCR
freq = freq*16; // PLL Mul=16
}
else{
freq = freq*12; // PLL Mul=12
}
pllsel = (CGC->MCKC>>1)&0x03; // PLL div in MCKC
if (pllsel==0){
pllsel = pllsel + 1; // 00b: Div=1
}
else if(pllsel==3){
pllsel = (pllsel+1) * 2; // 11b: (Div+1)*2=8
}
else{
pllsel = pllsel * 2; // 01~10b: (Div*2)=2or4
}
freq = freq/pllsel;
}
//else{ /* CGC->MCKC&0x80 = 0: PLL Off */
//freq = CLK_GetfIHFreq(); /* Get fIH frequency */
//}
}
return(freq);
}
__WEAK void SystemCoreClockUpdate (void) /* Get Core Clock Frequency */
{
/* ToDo: add code to calculate the system frequency based upon the current
register settings.
This function can be used to retrieve the system core clock frequeny
after user changed register sittings. */
SystemCoreClock = CLK_GetCoreFreq();
}
void SystemInit (void)
{
/* ToDo: add code to initialize the system
do not use global variables because this function is called before
reaching pre-main. RW section maybe overwritten afterwards. */
/* RAM Parity Error Reset Disable */
SAF->RPECTL = 0x80U;
CGC->WDTCFG0 = 0x1A;
CGC->WDTCFG1 = 0x2B;
CGC->WDTCFG2 = 0x3C;
CGC->WDTCFG3 = 0x4D;
DBG->DBGSTOPCR = 0;
SystemCoreClock = CLK_GetCoreFreq();
/* NVIC Clear Pending IRQ */
NVIC->ICPR[0U] = 0xFFFFFFFF;
/* NVIC Enable IRQs */
NVIC->ISER[0U] = 0xFFFFFFFF;
/* NVIC Lower Priority */
NVIC->IP[0U] = 0xC0C0C0C0;
NVIC->IP[1U] = 0xC0C0C0C0;
NVIC->IP[2U] = 0xC0C0C0C0;
NVIC->IP[3U] = 0xC0C0C0C0;
NVIC->IP[4U] = 0xC0C0C0C0;
NVIC->IP[5U] = 0xC0C0C0C0;
NVIC->IP[6U] = 0xC0C0C0C0;
NVIC->IP[7U] = 0xC0C0C0C0;
/* restart watchdog timer */
WDT->WDTE = 0xACU;
}
Firmware/Project/Cmsemicon/BAT32A279/MDK_ARM/RTE/Device/BAT32A239KK64FB/userdefine.h deleted 100644 → 0
View file @ 6e32a063
/***********************************************************************************************************************
* Copyright (C) All rights reserved.
***********************************************************************************************************************/
/***********************************************************************************************************************
* @file userdefine.h
* @brief This file includes user definition.
* @version 1.0.0
* @date 2019/12/24
***********************************************************************************************************************/
#ifndef _USER_DEF_H
#define _USER_DEF_H
/***********************************************************************************************************************
User definitions
***********************************************************************************************************************/
#ifndef __TYPEDEF__
typedef unsigned short MD_STATUS;
#define HAS_BOOTLOADER (1u) // 仅仿真App时设置为0
#define APP_BASE (0x00008000ul)
/* Status list definition */
#define MD_STATUSBASE (0x00U)
#define MD_OK (MD_STATUSBASE + 0x00U) /* register setting OK */
#define MD_SPT (MD_STATUSBASE + 0x01U) /* IIC stop */
#define MD_NACK (MD_STATUSBASE + 0x02U) /* IIC no ACK */
#define MD_BUSY1 (MD_STATUSBASE + 0x03U) /* busy 1 */
#define MD_BUSY2 (MD_STATUSBASE + 0x04U) /* busy 2 */
#define MD_OVERRUN (MD_STATUSBASE + 0x05U) /* IIC OVERRUN occur */
/* Error list definition */
#define MD_ERRORBASE (0x80U)
#define MD_ERROR (MD_ERRORBASE + 0x00U) /* error */
#define MD_ARGERROR (MD_ERRORBASE + 0x01U) /* error agrument input error */
#define MD_ERROR1 (MD_ERRORBASE + 0x02U) /* error 1 */
#define MD_ERROR2 (MD_ERRORBASE + 0x03U) /* error 2 */
#define MD_ERROR3 (MD_ERRORBASE + 0x04U) /* error 3 */
#define MD_ERROR4 (MD_ERRORBASE + 0x05U) /* error 4 */
#define MD_ERROR5 (MD_ERRORBASE + 0x06U) /* error 5 */
#endif
#define TRMW *((volatile uint8_t *)(0x40021C08))
#define TRMR *((volatile uint8_t *)(0x40021C0C))
#define TRMT *((volatile uint8_t *)(0x40021C10))
/***********************************************************************************************************************
Macro definitions for Clock
***********************************************************************************************************************/
#define CPU_CLOCK_FREQ 64000000UL//64MHz clock frequency
#define PLL_CLOCK
/***********************************************************************************************************************
Macro definitions for CAN
***********************************************************************************************************************/
#define CAN0_USE
#define CAN1_USE
#define CAN_REC_MASK1 0x1fffffffU
#define CAN_REC_MASK2 0x1fffffffU
#define CAN_REC_MASK3 0x1fffffffU
#define CAN_REC_MASK4 0x1fffffffU
/***********************************************************************************************************************
Macro definitions of SCI usage:
Each channel of SCI has three functions: UART, SPI, and IIC. You can only choose one function to use.
***********************************************************************************************************************/
/* ToDo: You can only define ONE of the following THREE MACROs according to your application */
#define USE_SCI_UART0_TX /*! Using CH0 of SCI0 as UART Transmitter */
//#define USE_SCI_SPI00 /*! Using CH0 of SCI0 as SPI Transmitter or Receiver */
//#define USE_SCI_IIC00 /*! Using CH0 of SCI0 as IIC Transmitter or Receiver */
/* ToDo: You can only define ONE of the following THREE MACROs according to your application */
#define USE_SCI_UART0_RX /*! Using CH1 of SCI0 as UART Receiver */
//#define USE_SCI_SPI01 /*! Using CH1 of SCI0 as SPI Transmitter or Receiver */
//#define USE_SCI_IIC01 /*! Using CH1 of SCI0 as IIC Transmitter or Receiver */
/* ToDo: You can only define ONE of the following THREE MACROs according to your application */
#define USE_SCI_UART1_TX /*! Using CH2 of SCI0 as UART Transmitter */
//#define USE_SCI_SPI10 /*! Using CH2 of SCI0 as SPI Transmitter or Receiver */
//#define USE_SCI_IIC10 /*! Using CH2 of SCI0 as IIC Transmitter or Receiver */
/* ToDo: You can only define ONE of the following THREE MACROs according to your application */
#define USE_SCI_UART1_RX /*! Using CH3 of SCI0 as UART Receiver */
//#define USE_SCI_SPI11 /*! Using CH3 of SCI0 as SPI Transmitter or Receiver */
//#define USE_SCI_IIC11 /*! Using CH3 of SCI0 as IIC Transmitter or Receiver */
/* ToDo: You can only define ONE of the following THREE MACROs according to your application */
//#define USE_SCI_UART2_TX /*! Using CH0 of SCI1 as UART Transmitter */
//#define USE_SCI_SPI20 /*! Using CH0 of SCI1 as SPI Transmitter or Receiver */
#define USE_SCI_IIC20 /*! Using CH0 of SCI1 as IIC Transmitter or Receiver */
/* ToDo: You can only define ONE of the following THREE MACROs according to your application */
//#define USE_SCI_UART2_RX /*! Using CH1 of SCI1 as UART Receiver */
//#define USE_SCI_SPI21 /*! Using CH1 of SCI1 as SPI Transmitter or Receiver */
#define USE_SCI_IIC21 /*! Using CH1 of SCI1 as IIC Transmitter or Receiver */
/* ToDo: You can only define ONE of the following THREE MACROs according to your application */
#define USE_SCI_UART3_TX /*! Using CH0 of SCI2 as UART Transmitter */
//#define USE_SCI_SPI30 /*! Using CH0 of SCI2 as SPI Transmitter or Receiver */
//#define USE_SCI_IIC30 /*! Using CH0 of SCI2 as IIC Transmitter or Receiver */
/* ToDo: You can only define ONE of the following THREE MACROs according to your application */
#define USE_SCI_UART3_RX /*! Using CH1 of SCI2 as UART Receiver */
//#define USE_SCI_SPI31 /*! Using CH1 of SCI2 as SPI Transmitter or Receiver */
//#define USE_SCI_IIC31 /*! Using CH1 of SCI2 as IIC Transmitter or Receiver */
/***********************************************************************************************************************
DMA Control Data Set definitions
***********************************************************************************************************************/
#define SPI00_WITH_DMA
#define CTRL_DATA_SPI00 0
//#define SPI01_WITH_DMA
//#define CTRL_DATA_SPI01 2
#define SPI10_WITH_DMA
#define CTRL_DATA_SPI10 4
#define SPI11_WITH_DMA
#define CTRL_DATA_SPI11 6
//#define SPI20_WITH_DMA
//#define CTRL_DATA_SPI20 8
//#define SPI21_WITH_DMA
//#define CTRL_DATA_SPI21 10
#define ADC_WITH_DMA
#define CTRL_DATA_ADC 12
#define DAC_WITH_DMA
#define CTRL_DATA_DAC 14
#define DMA_CHANNEL_NUMBER 4
#define DMA_VECTOR_BASE_SIZE 64
#define DMA_VECTOR_SIZE (DMA_VECTOR_BASE_SIZE+16*DMA_CHANNEL_NUMBER)
/** @addtogroup Peripherals_Port_Setting_Definations
* @{
*/
/* ================================================================================================================== */
/* ================ TM40 ================ */
/* ================================================================================================================== */
/**
* @brief TM40 TI00~3 and TO00~3 Port Setting (Alternative to fixed ports)
*/
#define TI00_PORT_SETTING() do{ \
PORT->PM0 |= (1 << 0); /* P00 is used as TI00 input */ \
PORT->PMC0 &= ~(1 << 0); /* P00 is digital function */ \
}while(0)
#define TI01_PORT_SETTING() do{ \
PORT->PM1 |= (1 << 6); /* P16 is used as TI01 input */ \
}while(0)
#define TI02_PORT_SETTING() do{ \
PORT->PM1 |= (1 << 7); /* P17 is used as TI02 input */ \
}while(0)
#define TI03_PORT_SETTING() do{ \
PORT->PM3 |= (1 << 1); /* P31 is used as TI03 input */ \
}while(0)
#define TO00_PORT_SETTING() do{ \
PORT->P0 &= ~(1 << 1); /* P01 output low level */ \
PORT->PM0 &= ~(1 << 1); /* P01 is used as TO00 output */ \
PORT->PMC0 &= ~(1 << 1); /* P01 is digital function */ \
}while(0)
#define TO01_PORT_SETTING() do{ \
PORT->P1 &= ~(1 << 6); /* P16 output low level */ \
PORT->PM1 &= ~(1 << 6); /* P16 is used as TO01 output */ \
}while(0)
#define TO02_PORT_SETTING() do{ \
PORT->P1 &= ~(1 << 7); /* P17 output low level */ \
PORT->PM1 &= ~(1 << 7); /* P17 is used as TO02 output */ \
}while(0)
#define TO03_PORT_SETTING() do{ \
PORT->P3 &= ~(1 << 1); /* P31 output low level */ \
PORT->PM3 &= ~(1 << 1); /* P31 is used as TO03 output */ \
}while(0)
/* ================================================================================================================== */
/* ================ TM81 ================ */
/* ================================================================================================================== */
/**
* @brief TM81 TI10~3 and TO10~3 Port Setting (Alternative to fixed ports)
*/
#define TI10_PORT_SETTING() do{ \
PORT->PM6 |= (1 << 4); /* P64 is used as TI10 input */ \
}while(0)
#define TI11_PORT_SETTING() do{ \
PORT->PM6 |= (1 << 5); /* P65 is used as TI11 input */ \
}while(0)
#define TI12_PORT_SETTING() do{ \
PORT->PM6 |= (1 << 6); /* P66 is used as TI12 input */ \
}while(0)
#define TI13_PORT_SETTING() do{ \
PORT->PM6 |= (1 << 7); /* P67 is used as TI13 input */ \
}while(0)
#define TO10_PORT_SETTING() do{ \
PORT->P6 &= ~(1 << 4); /* P64 output low level */ \
PORT->PM6 &= ~(1 << 4); /* P64 is used as TO10 output */ \
}while(0)
#define TO11_PORT_SETTING() do{ \
PORT->P6 &= ~(1 << 5); /* P65 output low level */ \
PORT->PM6 &= ~(1 << 5); /* P65 is used as TO11 output */ \
}while(0)
#define TO12_PORT_SETTING() do{ \
PORT->P6 &= ~(1 << 6); /* P66 output low level */ \
PORT->PM6 &= ~(1 << 6); /* P66 is used as TO12 output */ \
}while(0)
#define TO13_PORT_SETTING() do{ \
PORT->P6 &= ~(1 << 7); /* P67 output low level */ \
PORT->PM6 &= ~(1 << 7); /* P67 is used as TO13 output */ \
}while(0)
#define TI14_PORT_SETTING() do{ \
PORT->PM10 |= (1 << 0); /* P100 is used as TI14 input */ \
PORT->PMC10 &= ~(1 << 0); /* P100 is digital function */ \
}while(0)
#define TI15_PORT_SETTING() do{ \
PORT->PM1 |= (1 << 0); /* P110 is used as TI15 input */ \
}while(0)
#define TI16_PORT_SETTING() do{ \
PORT->PM11 |= (1 << 1); /* P111 is used as TI16 input */ \
}while(0)
#define TI17_PORT_SETTING() do{ \
PORT->PM0 |= (1 << 5); /* P05 is used as TI17 input */ \
}while(0)
#define TO14_PORT_SETTING() do{ \
PORT->P10 &= ~(1 << 0); /* P100 output low level */ \
PORT->PM10 &= ~(1 << 0); /* P100 is used as TO14 output */ \
PORT->PMC10 &= ~(1 << 0); /* P100 is digital function */ \
}while(0)
#define TO15_PORT_SETTING() do{ \
PORT->P11 &= ~(1 << 0); /* P110 output low level */ \
PORT->PM11 &= ~(1 << 0); /* P110 is used as TO15 output */ \
}while(0)
#define TO16_PORT_SETTING() do{ \
PORT->P11 &= ~(1 << 1); /* P111 output low level */ \
PORT->PM11 &= ~(1 << 1); /* P111 is used as TO16 output */ \
}while(0)
#define TO17_PORT_SETTING() do{ \
PORT->P0 &= ~(1 << 5); /* P05 output low level */ \
PORT->PM0 &= ~(1 << 5); /* P05 is used as TO17 output */ \
}while(0)
/* ================================================================================================================== */
/* ================ TMA ================ */
/* ================================================================================================================== */
/**
* @brief TAIO Port Setting (Alternative to 4 group ports)
*/
/* ToDo: You can allocate the TAIO to P01, P31, P41, or P06 with PIOR11 and PIOR10 register */
#define TAIO_PORT_SETTING() do{ \
PORT->PIOR1 |= (0 << 0); /* allocate TAIO to P01 */ \
PORT->P0 &= ~(1 << 1); /* P01 output low level */ \
PORT->PM0 &= ~(1 << 1); /* P01 is used as TAIO output */ \
PORT->POM0 &= ~(1 << 1); /* P01 is push-pull output mode */ \
}while(0)
/* ToDo: You can allocate the TAIO to P01, P31, P41, or P06 with PIOR11 and PIOR10 register */
#define TAI_PORT_SETTING() do{ \
PORT->PIOR1 |= (0 << 0); /* allocate TAIO to P01 */ \
PORT->PM0 |= (1 << 1); /* P01 is used as TAIO input */ \
}while(0)
/* ToDo: You can allocate the TAO to P30, P50, or P00 with PIOR13 and PIOR12 register */
#define TAO_PORT_SETTING() do{ \
PORT->PIOR1 |= (0 << 2); /* allocate TAO to P30 */ \
PORT->P3 &= ~(1 << 0); /* P30 output low level */ \
PORT->PM3 &= ~(1 << 0); /* P30 is used as TAO output */ \
PORT->POM3 &= ~(1 << 0); /* P30 is push-pull output mode */ \
}while(0)
/* ================================================================================================================== */
/* ================ TMB ================ */
/* ================================================================================================================== */
/**
* @brief TMB Port Setting（Alternative to fixed port)
*/
#define TBCLK0_PORT_SETTING() do{ \
PORT->PM0 |= (1 << 0); /* P00 is used as TBCLK0 input */ \
}while(0)
#define TBCLK1_PORT_SETTING() do{ \
PORT->PM0 |= (1 << 1); /* P01 is used as TBCLK1 input */ \
}while(0)
#define TBI0_PORT_SETTING() do{ \
PORT->PM5 |= (1 << 0); /* P50 is used as TBIO0 input */ \
}while(0)
#define TBI1_PORT_SETTING() do{ \
PORT->PM5 |= (1 << 1); /* P51 is used as TBIO1 input */ \
}while(0)
#define TBO0_PORT_SETTING() do{ \
PORT->P5 &= ~(1 << 0); /* P50 output low level */ \
PORT->PM5 &= ~(1 << 0); /* P50 is used as TBIO0 output */ \
PORT->POM5 &= ~(1 << 0); /* P50 is push-pull output mode */ \
}while(0)
#define TBO1_PORT_SETTING() do{ \
PORT->P5 &= ~(1 << 1); /* P51 output low level */ \
PORT->PM5 &= ~(1 << 1); /* P51 is used as TBIO1 output */ \
PORT->POM5 &= ~(1 << 1); /* P51 is push-pull output mode */ \
}while(0)
/* ================================================================================================================== */
/* ================ TMM ================ */
/* ================================================================================================================== */
/**
* @brief TMM Port Setting（Alternative to 3 group ports)
*/
#define TMCLK_PORT_SETTING() do{ \
PORT->PM1 |= (1 << 7); /* P17 is used as TMCLK input */ \
}while(0)
#define TMIA0_PORT_SETTING() do{ \
PORT->PM1 |= (1 << 7); /* P17 is used as TMIOA0 input */ \
}while(0)
/* ToDo: You can allocate the TMIOB0 to P14, P12, or P15 with PIOR37 and PIOR36 register */
#define TMIB0_PORT_SETTING() do{ \
PORT->PM1 |= (1 << 4); /* P14 is used as TMIOB0 input */ \
}while(0)
#define TMIC0_PORT_SETTING() do{ \
PORT->PM1 |= (1 << 6); /* P16 is used as TMIOC0 input */ \
}while(0)
/* ToDo: You can allocate the TMIOD0 to P15, P15, or P14 with PIOR37 and PIOR36 register */
#define TMID0_PORT_SETTING() do{ \
PORT->PM1 |= (1 << 5); /* P15 is used as TMIOD0 input */ \
}while(0)
/* ToDo: You can allocate the TMIOA1 to P12, P11, or P13 with PIOR37 and PIOR36 register */
#define TMIA1_PORT_SETTING() do{ \
PORT->PM1 |= (1 << 2); /* P12 is used as TMIOA1 input */ \
}while(0)
/* ToDo: You can allocate the TMIOB1 to P10, P10, or P12 with PIOR37 and PIOR36 register */
#define TMIB1_PORT_SETTING() do{ \
PORT->PM1 |= (1 << 0); /* P10 is used as TMIOB1 input */ \
}while(0)
/* ToDo: You can allocate the TMIOC1 to P13, P14, or P11 with PIOR37 and PIOR36 register */
#define TMIC1_PORT_SETTING() do{ \
PORT->PM1 |= (1 << 3); /* P13 is used as TMIOC1 input */ \
}while(0)
/* ToDo: You can allocate the TMIOD1 to P11, P13, or P10 with PIOR37 and PIOR36 register */
#define TMID1_PORT_SETTING() do{ \
PORT->PM1 |= (1 << 1); /* P11 is used as TMIOD1 input */ \
}while(0)
#define TMOA0_PORT_SETTING() do{ \
PORT->P1 &= ~(1 << 7); /* P17 output low level */ \
PORT->PM1 &= ~(1 << 7); /* P17 is used as TMIOA0 output */ \
PORT->POM1 &= ~(1 << 7); /* P17 is push-pull output mode */ \
}while(0)
#define TMOB0_PORT_SETTING() do{ \
PORT->P1 &= ~(1 << 4); /* P14 output low level */ \
PORT->PM1 &= ~(1 << 4); /* P14 is used as TMIOB0/U+ output */ \
PORT->POM1 &= ~(1 << 4); /* P14 is push-pull output mode */ \
}while(0)
#define TMOC0_PORT_SETTING() do{ \
PORT->P1 &= ~(1 << 6); /* P16 output low level */ \
PORT->PM1 &= ~(1 << 6); /* P16 is used as TMIOC0 output */ \
PORT->POM1 &= ~(1 << 6); /* P16 is push-pull output mode */ \
}while(0)
#define TMOD0_PORT_SETTING() do{ \
PORT->P1 &= ~(1 << 5); /* P15 output low level */ \
PORT->PM1 &= ~(1 << 5); /* P15 is used as TMIOD0/U- output */ \
PORT->POM1 &= ~(1 << 5); /* P15 is push-pull output mode */ \
}while(0)
#define TMOA1_PORT_SETTING() do{ \
PORT->P1 &= ~(1 << 2); /* P12 output low level */ \
PORT->PM1 &= ~(1 << 2); /* P12 is used as TMIOA1/V+ output */ \
PORT->POM1 &= ~(1 << 2); /* P12 is push-pull output mode */ \
}while(0)
#define TMOB1_PORT_SETTING() do{ \
PORT->P1 &= ~(1 << 0); /* P10 output low level */ \
PORT->PM1 &= ~(1 << 0); /* P10 is used as TMIOB1/W+ output */ \
PORT->POM1 &= ~(1 << 0); /* P10 is push-pull output mode */ \
PORT->PMC1 &= ~(1 << 0); /* P10 is digital function */ \
}while(0)
#define TMOC1_PORT_SETTING() do{ \
PORT->P1 &= ~(1 << 3); /* P13 output low level */ \
PORT->PM1 &= ~(1 << 3); /* P13 is used as TMIOC1/V- output */ \
PORT->POM1 &= ~(1 << 3); /* P13 is push-pull output mode */ \
}while(0)
#define TMOD1_PORT_SETTING() do{ \
PORT->P1 &= ~(1 << 1); /* P11 output low level */ \
PORT->PM1 &= ~(1 << 1); /* P11 is used as TMIOD1/W- output */ \
PORT->POM1 &= ~(1 << 1); /* P11 is push-pull output mode */ \
PORT->PMC1 &= ~(1 << 1); /* P11 is digital function */ \
}while(0)
#define MTR_PORT_UP_SET() do{ \
PORT->P1 |= (1 << 4); /* TMIOB0/U+ output H level */ \
}while(0)
#define MTR_PORT_UP_CLR() do{ \
PORT->P1 &= ~(1 << 4); /* TMIOB0/U+ output L level */ \
}while(0)
#define MTR_PORT_VP_SET() do{ \
PORT->P1 |= (1 << 2); /* TMIOA1/V+ output H level */ \
}while(0)
#define MTR_PORT_VP_CLR() do{ \
PORT->P1 &= ~(1 << 2); /* TMIOA1/V+ output L level */ \
}while(0)
#define MTR_PORT_WP_SET() do{ \
PORT->P1 |= (1 << 0); /* TMIOB1/W+ output H level */ \
}while(0)
#define MTR_PORT_WP_CLR() do{ \
PORT->P1 &= ~(1 << 0); /* TMIOB1/W+ output L level */ \
}while(0)
#define MTR_PORT_UN_SET() do{ \
PORT->P1 |= (1 << 5); /* TMIOD0/U- output H level */ \
}while(0)
#define MTR_PORT_UN_CLR() do{ \
PORT->P1 &= ~(1 << 5); /* TMIOD0/U- output L level */ \
}while(0)
#define MTR_PORT_VN_SET() do{ \
PORT->P1 |= (1 << 3); /* TMIOC1/V- output H level */ \
}while(0)
#define MTR_PORT_VN_CLR() do{ \
PORT->P1 &= ~(1 << 3); /* TMIOC1/V- output L level */ \
}while(0)
#define MTR_PORT_WN_SET() do{ \
PORT->P1 |= (1 << 1); /* TMIOD1/W- output H level */ \
}while(0)
#define MTR_PORT_WN_CLR() do{ \
PORT->P1 &= ~(1 << 1); /* TMIOD1/W- output L level */ \
}while(0)
/* ================================================================================================================== */
/* ================ RTC1HZ ================ */
/* ================================================================================================================== */
/**
* @brief RTC1HZ Port Setting（Alternative to fixed port)
*/
#define RTC1HZ_PORT_SETTING() do{ \
PORT->P3 &= ~(1 << 0); /* P30 output low level */ \
PORT->PM3 &= ~(1 << 0); /* P30 is used as RTC1HZ output */ \
PORT->POM3 &= ~(1 << 0); /* P30 is push-pull output mode */ \
}while(0)
/* ================================================================================================================== */
/* ================ CLKBUZ ================ */
/* ================================================================================================================== */
/**
* @brief CLKBUZ Port Setting（Alternative to 2 group ports)
*/
#if 1
/* ToDo: You can allocate the CLKBUZ0 to P140 or P31 with PIOR03 register */
#define CLKBUZ0_PORT_SETTING() do{ \
PORT->PIOR0 &= ~(1 << 3); /* allocate CLKBUZ0 to P140 */ \
PORT->P14 &= ~(1 << 0); /* P140 output low level */ \
PORT->PM14 &= ~(1 << 0); /* P140 is used as CLKBUZ0 output */ \
}while(0)
#else
/* ToDo: You can allocate the CLKBUZ0 to P140 or P31 with PIOR03 register */
#define CLKBUZ0_PORT_SETTING() do{ \
PORT->PIOR0 |= (1 << 3); /* allocate CLKBUZ0 to P31 */ \
PORT->P3 &= ~(1 << 1); /* P31 output low level */ \
PORT->PM3 &= ~(1 << 1); /* P31 is used as CLKBUZ0 output */ \
}while(0)
#endif
#if 1
/* ToDo: You can allocate the CLKBUZ1 to P141 or P55 with PIOR04 register */
#define CLKBUZ1_PORT_SETTING() do{ \
PORT->PIOR0 &= ~(1 << 4); /* allocate CLKBUZ1 to P141 */ \
PORT->P14 &= ~(1 << 1); /* P141 output low level */ \
PORT->PM14 &= ~(1 << 1); /* P141 is used as CLKBUZ1 output */ \
}while(0)
#else
/* ToDo: You can allocate the CLKBUZ1 to P141 or P55 with PIOR04 register */
#define CLKBUZ1_PORT_SETTING() do{ \
PORT->PIOR0 |= (1 << 4); /* allocate CLKBUZ1 to P55 */ \
PORT->P5 &= ~(1 << 5); /* P55 output low level */ \
PORT->PM5 &= ~(1 << 5); /* P55 is used as CLKBUZ1 output */ \
}while(0)
#endif
/* ================================================================================================================== */
/* ================ ADC ================ */
/* ================================================================================================================== */
/**
* @brief ADC Port Setting (Alternate to fixed ports)
*/
/* ToDo: Please comment out the following unused ANIx setting according to your application needs. */
//#define ADC_PORT_SETTING() do{ \
// PORT->PMC2 |= (1 << 0); /* Set ANI0(P20) pin: It is necessary for ADC_VREF_AVREFP_AVREFM, used as AVREFP */ \
// PORT->PMC2 |= (1 << 1); /* Set ANI1(P21) pin: It is necessary for ADC_VREF_AVREFP_AVREFM, used as AVREFM */ \
// PORT->PMC2 |= (1 << 2); /* Set ANI2(P22) pin */ \
// PORT->PMC2 |= (1 << 3); /* Set ANI3(P23) pin */ \
// PORT->PMC2 |= (1 << 4); /* Set ANI4(P24) pin */ \
// PORT->PMC2 |= (1 << 5); /* Set ANI5(P25) pin */ \
// PORT->PMC2 |= (1 << 6); /* Set ANI6(P26) pin */ \
// PORT->PMC2 |= (1 << 7); /* Set ANI7(P27) pin */ \
// PORT->PMC1 |= (1 << 1); /* Set ANI8(P11) pin */ \
// PORT->PMC1 |= (1 << 0); /* Set ANI9(P10) pin */ \
// PORT->PMC0 |= (1 << 3); /* Set ANI10(P03) pin */ \
// PORT->PMC0 |= (1 << 2); /* Set ANI11(P02) pin */ \
// PORT->PMC14|= (1 << 7); /* Set ANI12(P147) pin */ \
// PORT->PMC0 |= (1 << 4); /* Set ANI13(P04) pin */ \
// PORT->PMC12|= (1 << 0); /* Set ANI14(P120) pin */ \
// PORT->PMC14|= (1 << 6); /* Set ANI15(P146) pin */ \
//}while(0)
#define ADC_PORT_SETTING() do{ \
PORT->PMC2 |= (1 << 0); /* Set ANI0(P20) pin: It is necessary for ADC_VREF_AVREFP_AVREFM, used as AVREFP */ \
PORT->PMC2 |= (1 << 1); /* Set ANI1(P21) pin: It is necessary for ADC_VREF_AVREFP_AVREFM, used as AVREFM */ \
PORT->PMC2 |= (1 << 2); /* Set ANI2(P22) pin */ \
PORT->PMC2 |= (1 << 3); /* Set ANI3(P23) pin */ \
}while(0)
/* ================================================================================================================== */
/* ================ DAC ================ */
/* ================================================================================================================== */
/**
* @brief DAC Port Setting (Alternate to fixed ports)
*/
#define DAC0_PORT_SETTING() do{ \
PORT->PMC2 |= (1 << 2); /* Set ANO0(P22) pin */ \
}while(0)
#define DAC1_PORT_SETTING() do{ \
PORT->PMC2 |= (1 << 3); /* Set ANO1(P23) pin */ \
}while(0)
/* ================================================================================================================== */
/* ================ CMP ================ */
/* ================================================================================================================== */
/**
* @brief CMP Port Setting (Analog input alternate to fixed ports, digital output alternate to 2 group ports)
*/
#if 1
/* ToDo: You can allocate the VCOUT0 to P120 or P71 with PIOR20 register */
#define VCOUT0_PORT_SETTING() do { \
PORT->PIOR3 |= (1 << 1); /* VCOUT0 output enable */ \
PORT->PIOR2 &= ~(1 << 0); /* allocate VCOUT0 to P120 */ \
PORT->P12 &= ~(1 << 0); /* P120 output low level */ \
PORT->PM12 &= ~(1 << 0); /* VCOUT0 output to P120 */ \
PORT->PMC12 &= ~(1 << 0); /* P120 is digital function */ \
}while(0)
#else
/* ToDo: You can allocate the VCOUT0 to P120 or P71 with PIOR20 register */
#define VCOUT0_PORT_SETTING() do { \
PORT->PIOR3 |= (1 << 1); /* VCOUT0 output enable */ \
PORT->PIOR2 |= (1 << 0); /* allocate VCOUT0 to P71 */ \
PORT->P7 &= ~(1 << 1); /* P71 output low level */ \
PORT->PM7 &= ~(1 << 1); /* VCOUT0 output to P71 */ \
}while(0)
#endif
#if 1
/* ToDo: You can allocate the VCOUT1 to P31 or P70 with PIOR21 register */
#define VCOUT1_PORT_SETTING() do { \
PORT->PIOR3 |= (1 << 2); /* VCOUT1 output enable */ \
PORT->PIOR2 &= ~(1 << 1); /* allocate VCOUT1 to P31 */ \
PORT->P3 &= ~(1 << 1); /* P31 output low level */ \
PORT->PM3 &= ~(1 << 1); /* VCOUT1 output to P31 */ \
}while(0)
#else
#define VCOUT1_PORT_SETTING() do { \
PORT->PIOR3 |= (1 << 2); /* VCOUT1 output enable */ \
PORT->PIOR2 |= (1 << 1); /* allocate VCOUT1 to P70 */ \
PORT->P7 &= ~(1 << 0); /* P70 output low level */ \
PORT->PM7 &= ~(1 << 0); /* VCOUT1 output to P70 */ \
}while(0)
#endif
/* ToDo: Please comment out the VREF0 setting if don't used VREF0 as negative(-) side input of CMP */
#define CMP0_PORT_SETTING() do{ \
PORT->PMC2 |= (1 << 2); /* Set VCIN0(P22) pin */ \
PORT->PMC14 |= (1 << 7); /* Set VREF0(P147) pin */ \
VCOUT0_PORT_SETTING(); /* ToDo: Please delete me if you don't output VCOUT0 signal to port */ \
}while(0)
/* ToDo: Please comment out the VCINxx setting if don't used it as positive(+) side input of CMP */
#define CMP1_PORT_SETTING() do{ \
PORT->PMC0 |= (1 << 2); /* Set VCIN10(P02) pin */ \
PORT->PMC0 |= (1 << 3); /* Set VCIN11(P03) pin */ \
PORT->PMC2 |= (1 << 0); /* Set VCIN12(P20) pin */ \
PORT->PMC2 |= (1 << 1); /* Set VCIN13(P21) pin */ \
VCOUT1_PORT_SETTING(); /* ToDo: Please delete me if you don't output VCOUT1 signal to port */ \
}while(0)
/* ================================================================================================================== */
/* ================ PGA ================ */
/* ================================================================================================================== */
/**
* @brief PGA Port Setting (Alternate to fixed ports)
*/
#define PGA0O_PORT_SETTING() do { \
PORT->PMC2 |= (1 << 0); /* PGA0O output to P20 */ \
}while(0)
#define PGA1O_PORT_SETTING() do { \
PORT->PMC2 |= (1 << 1); /* PGA1O output to P21 */ \
}while(0)
#define PGA0IN_PORT_SETTING() do { \
PORT->PMC2 |= (1 << 2); /* PGA0IN input from P22 */ \
}while(0)
#define PGA0GND_PORT_SETTING() do { \
PORT->PMC2 |= (1 << 3); /* PGA0GND input from P23 */ \
}while(0)
#define PGA1IN_PORT_SETTING() do { \
PORT->PMC2 |= (1 << 4); /* PGA1IN input from P24 */ \
}while(0)
#define PGA1GND_PORT_SETTING() do { \
PORT->PMC2 |= (1 << 5); /* PGA1GND input from P25 */ \
}while(0)
/* ================================================================================================================== */
/* ================ SCI0 ================ */
/* ================================================================================================================== */
/* ToDo: You can allocate the TXD0, RXD0, SCLK00, SDI00, SDO00, SCL00 and SDA00 to the following ports with PIOR register */
/* PIOR35 PIOR34 PIOR01 : TXD0 RXD0 SCLK00 SDO00 SDI00 SCL00 SDA00
* 0 0 0 : P51 P50 P30 P51 P50 P30 P50 # default setting
* 0 0 1 : P17 P16 P55 P17 P16 - -
* 0 1 X : P40 P137 - - - - -
* 1 X X : P12 P11 - - - - -
*/
/**
* @brief UART0 Port Setting（Alternative to 4 group ports)
*/
#if 1
/* ToDo: You can allocate the TXD0 to P51, P17, P40 or P12 with PIOR35, PIOR43 and PIOR01 register */
#define TXD0_PORT_SETTING() do{ \
PORT->PIOR0 &= ~(1 << 1); /* allocate TXD0 to P51 */ \
PORT->P5 |= (1 << 1); /* P51 output high level */ \
PORT->PM5 &= ~(1 << 1); /* P51 is used as TXD0 output */ \
PORT->POM5 &= ~(1 << 1); /* P51 is push-pull output mode */ \
}while(0)
/* ToDo: You can allocate the RXD0 to P50, P16, P137 or P11 with PIOR35, PIOR43 and PIOR01 register */
#define RXD0_PORT_SETTING() do{ \
PORT->PIOR0 &= ~(1 << 1); /* allocate RXD0 to P50 */ \
PORT->PM5 |= (1 << 0); /* P50 is used as RXD0 input */ \
}while(0)
#else
/* ToDo: You can allocate the TXD0 to P51, P17, P40 or P12 with PIOR35, PIOR43 and PIOR01 register */
#define TXD0_PORT_SETTING() do{ \
PORT->PIOR0 |= (1 << 1); /* allocate TXD0 to P17 */ \
PORT->P1 |= (1 << 7); /* P17 output high level */ \
PORT->PM1 &= ~(1 << 7); /* P17 is used as TXD0 output */ \
PORT->POM1 &= ~(1 << 7); /* P17 is push-pull output mode */ \
}while(0)
/* ToDo: You can allocate the RXD0 to P50, P16, P137 or P11 with PIOR35, PIOR43 and PIOR01 register */
#define RXD0_PORT_SETTING() do{ \
PORT->PIOR0 |= (1 << 1); /* allocate RXD0 to P16 */ \
PORT->PM1 |= (1 << 6); /* P16 is used as RXD0 input */ \
}while(0)
#endif
/**
* @brief SPI00 Port Setting（Alternative to 2 group ports)
*/
#define SS00_PORT_SETTING() do{ \
PORT->PM6 |= (1 << 2); /* P62 is used as SS00 input */ \
}while(0)
#define SS00_PORT_SET() do{ \
PORT->P6 |= (1 << 2); /* P62 output high level */ \
}while(0)
#define SS00_PORT_CLR() do{ \
PORT->P6 &= ~(1 << 2); /* P62 output low level */ \
}while(0)
/* ToDo: You can allocate the SCLK00 to P30 or P55 with PIOR01 register */
#define SCLKI00_PORT_SETTING() do{ \
PORT->PIOR0 &= ~(1 << 1); /* allocate SCLKI00 to P30 */ \
PORT->PM3 |= (1 << 0); /* P30 is used as SCLK00 input */ \
}while(0)
/* ToDo: You can allocate the SCLK00 to P30 or P55 with PIOR01 register */
#define SCLKO00_PORT_SETTING() do{ \
PORT->PIOR0 &= ~(1 << 1); /* allocate SCLKI00 to P30 */ \
PORT->P3 |= (1 << 0); /* P30 output high level */ \
PORT->PM3 &= ~(1 << 0); /* P30 is used as SCLK00 output */ \
PORT->POM3 &= ~(1 << 0); /* P30 is push-pull output mode */ \
}while(0)
/* ToDo: You can allocate the SDO00 to P51 or P17 with PIOR01 register */
#define SDO00_PORT_SETTING() do{ \
PORT->PIOR0 &= ~(1 << 1); /* allocate SDO00 to P51 */ \
PORT->P5 |= (1 << 1); /* P51 output high level */ \
PORT->PM5 &= ~(1 << 1); /* P51 is used as SDO00 output */ \
PORT->POM5 &= ~(1 << 1); /* P51 is push-pull output mode */ \
}while(0)
/* ToDo: You can allocate the SDI00 to P50 or P16 with PIOR01 register */
#define SDI00_PORT_SETTING() do{ \
PORT->PIOR0 &= ~(1 << 1); /* allocate SDI00 to P50 */ \
PORT->PM5 |= (1 << 0); /* P50 is used as SDI00 input */ \
}while(0)
/**
* @brief IIC00 Port Setting（Alternative to fixed port)
*/
#define SCL00_PORT_SETTING() do{ \
PORT->PIOR0 &= ~(1 << 1); /* allocate SCL00 to P30 */ \
PORT->P3 |= (1 << 0); /* P30 output high level */ \
PORT->PM3 &= ~(1 << 0); /* P30 is used as SCL00 output */ \
PORT->POM3 |= (1 << 0); /* P30 is N-ch open-drain output mode */ \
}while(0)
#define SDA00_PORT_SETTING() do{ \
PORT->PIOR0 &= ~(1 << 1); /* allocate SDA00 to P50 */ \
PORT->P5 |= (1 << 0); /* P50 output high level */ \
PORT->PM5 &= ~(1 << 0); /* P50 is used as SDA00 inout */ \
PORT->POM5 |= (1 << 0); /* P50 is N-ch open-drain output mode */ \
}while(0)
/**
* @brief SPI01 Port Setting (Alternative to fixed port)
*/
/* ToDo: You can allocate the SS01 to any desired pins */
#define SS01_PORT_SETTING() do{ \
PORT->P6 |= (1 << 2); /* P62 output high level */ \
PORT->PM6 &= ~(1 << 2); /* P62 is used as SS01 output */ \
}while(0)
/* ToDo: You can allocate the SS01 to any desired pins */
#define SS01_PORT_SET() do{ \
PORT->P6 |= (1 << 2); /* P62 output high level */ \
}while(0)
/* ToDo: You can allocate the SS01 to any desired pins */
#define SS01_PORT_CLR() do{ \
PORT->P6 &= ~(1 << 2); /* P62 output low level */ \
}while(0)
#define SCLKI01_PORT_SETTING() do{ \
PORT->PM7 |= (1 << 5); /* P75 is used as SCLK00 input */ \
}while(0)
#define SCLKO01_PORT_SETTING() do{ \
PORT->P7 |= (1 << 5); /* P75 output high level */ \
PORT->PM7 &= ~(1 << 5); /* P75 is used as SCLK00 output */ \
}while(0)
#define SDO01_PORT_SETTING() do{ \
PORT->P7 |= (1 << 3); /* P73 output high level */ \
PORT->PM7 &= ~(1 << 3); /* P73 is used as SDO01 output */ \
}while(0)
#define SDI01_PORT_SETTING() do{ \
PORT->PM7 |= (1 << 4); /* P74 is used as SDI01 input */ \
}while(0)
/**
* @brief IIC01 Port Setting (Alternative to fixed port)
*/
#define SCL01_PORT_SETTING() do{ \
PORT->P7 |= (1 << 5); /* P75 output high level */ \
PORT->PM7 &= ~(1 << 5); /* P75 is used as SCL01 output */ \
}while(0)
#define SDA01_PORT_SETTING() do{ \
PORT->P7 |= (1 << 4); /* P74 output high level */ \
PORT->PM7 &= ~(1 << 4); /* P74 is used as SDA01 inout */ \
PORT->POM7 |= (1 << 4); /* P74 is N-ch open-drain output mode */ \
}while(0)
/**
* @brief UART1 Port Setting (Alternative to fixed port)
*/
//#define TXD1_PORT_SETTING() do{ \
// PORT->P0 |= (1 << 2); /* P02 output high level */ \
// PORT->PM0 &= ~(1 << 2); /* P02 is used as TXD1 output */ \
// PORT->POM0 &= ~(1 << 2); /* P02 is push-pull output mode */ \
// PORT->PMC0 &= ~(1 << 2); /* P02 digital function */ \
//}while(0)
//#define RXD1_PORT_SETTING() do{ \
// PORT->PM0 |= (1 << 1); /* P01 is used as RXD1 input */ \
// PORT->PMC0 &= ~(1 << 1); /* P01 digital function */ \
//}while(0)
#define TXD1_PORT_SETTING() do{ \
PORT->P0 |= (1 << 2); /* P02 output high level */ \
PORT->PM0 &= ~(1 << 2); /* P02 is used as TXD1 output */ \
PORT->POM0 &= ~(1 << 2); /* P02 is push-pull output mode */ \
PORT->PMC0 &= ~(1 << 2); /* P02 digital function */ \
}while(0)
#define RXD1_PORT_SETTING() do{ \
PORT->PM0 |= (1 << 3); /* P03 is used as RXD1 input */ \
PORT->PMC0 &= ~(1 << 3); /* P03 digital function */ \
}while(0)
/**
* @brief SPI10 Port Setting (Alternative to fixed port)
*/
/* ToDo: You can allocate the SS10 to any desired pins */
#define SS10_PORT_SETTING() do{ \
PORT->P6 |= (1 << 2); /* P62 output high level */ \
PORT->PM6 &= ~(1 << 2); /* P62 is used as SS10 output */ \
}while(0)
/* ToDo: You can allocate the SS10 to any desired pins */
#define SS10_PORT_SET() do{ \
PORT->P6 |= (1 << 2); /* P62 output high level */ \
}while(0)
/* ToDo: You can allocate the SS10 to any desired pins */
#define SS10_PORT_CLR() do{ \
PORT->P6 &= ~(1 << 2); /* P62 output low level */ \
}while(0)
#define SCLKI10_PORT_SETTING() do{ \
PORT->PM0 |= (1 << 4); /* P04 is used as SCLK10 input */ \
PORT->PMC0 &= ~(1 << 4); /* P04 is digital function */ \
}while(0)
#define SCLKO10_PORT_SETTING() do{ \
PORT->P0 |= (1 << 4); /* P04 output high level */ \
PORT->PM0 &= ~(1 << 4); /* P04 is used as SCLK10 output */ \
PORT->POM0 &= ~(1 << 4); /* P04 is push-pull output mode */ \
PORT->PMC0 &= ~(1 << 4); /* P04 is digital function */ \
}while(0)
#define SDO10_PORT_SETTING() do{ \
PORT->P0 |= (1 << 2); /* P02 output high level */ \
PORT->PM0 &= ~(1 << 2); /* P02 is used as SDO10 output */ \
PORT->POM0 &= ~(1 << 2); /* P02 is push-pull output mode */ \
PORT->PMC0 &= ~(1 << 2); /* P02 is digital function */ \
}while(0)
#define SDI10_PORT_SETTING() do{ \
PORT->PM0 |= (1 << 3); /* P03 is used as SDI10 input */ \
PORT->PMC0 &= ~(1 << 3); /* P03 is digital function */ \
}while(0)
/**
* @brief IIC10 Port Setting (Alternative to fixed port)
*/
#define SCL10_PORT_SETTING() do{ \
PORT->P0 |= (1 << 4); /* P04 output */ \
PORT->PM0 &= ~(1 << 4); /* P04 is used as SCL10 output */ \
PORT->POM0 |= (1 << 4); /* P04 is N-ch open-drain output mode */ \
PORT->PMC0 &= ~(1 << 4); /* P04 is digital function */ \
}while(0)
#define SDA10_PORT_SETTING() do{ \
PORT->P0 |= (1 << 3); /* P03 output high level */ \
PORT->PM0 &= ~(1 << 3); /* P03 is used as SDA10 inout */ \
PORT->POM0 |= (1 << 3); /* P03 is N-ch open-drain output mode */ \
PORT->PMC0 &= ~(1 << 3); /* P03 is digital function */ \
}while(0)
/**
* @brief SPI11 Port Setting (Alternative to fixed port)
*/
/* ToDo: You can allocate the SS11 to any desired pins */
#define SS11_PORT_SETTING() do{ \
PORT->P6 |= (1 << 2); /* P62 output high level */ \
PORT->PM6 &= ~(1 << 2); /* P62 is used as SS11 output */ \
}while(0)
/* ToDo: You can allocate the SS11 to any desired pins */
#define SS11_PORT_SET() do{ \
PORT->P6 |= (1 << 2); /* P62 output high level */ \
}while(0)
/* ToDo: You can allocate the SS11 to any desired pins */
#define SS11_PORT_CLR() do{ \
PORT->P6 &= ~(1 << 2); /* P62 output low level */ \
}while(0)
#define SCLKI11_PORT_SETTING() do{ \
PORT->PM1 |= (1 << 0); /* P10 is used as SCLK11 input */ \
PORT->PMC1 &= ~(1 << 0); /* P10 is digital function */ \
}while(0)
#define SCLKO11_PORT_SETTING() do{ \
PORT->P1 |= (1 << 0); /* P10 output high level */ \
PORT->PM1 &= ~(1 << 0); /* P10 is used as SCLK11 output */ \
PORT->POM1 &= ~(1 << 0); /* P10 is push-pull output mode */ \
PORT->PMC1 &= ~(1 << 0); /* P10 is digital function */ \
}while(0)
#define SDO11_PORT_SETTING() do{ \
PORT->P1 |= (1 << 2); /* P12 output high level */ \
PORT->PM1 &= ~(1 << 2); /* P12 is used as SDO11 output */ \
PORT->POM1 &= ~(1 << 2); /* P12 is push-pull output mode */ \
PORT->PMC1 &= ~(1 << 2); /* P12 is digital function */ \
}while(0)
#define SDI11_PORT_SETTING() do{ \
PORT->PM1 |= (1 << 1); /* P11 is used as SDI11 input */ \
PORT->PMC1 &= ~(1 << 1); /* P11 is digital function */ \
}while(0)
/**
* @brief IIC11 Port Setting (Alternative to fixed port)
*/
#define SCL11_PORT_SETTING() do{ \
PORT->P1 |= (1 << 0); /* P10 output high level */ \
PORT->PM1 &= ~(1 << 0); /* P10 is used as SCL11 output */ \
PORT->POM1 |= (1 << 0); /* P10 is N-ch open-drain output mode */ \
PORT->PMC1 &= ~(1 << 0); /* P10 digital function */ \
}while(0)
#define SDA11_PORT_SETTING() do{ \
PORT->P1 |= (1 << 1); /* P11 output high level */ \
PORT->PM1 &= ~(1 << 1); /* P11 is used as SDA11 inout */ \
PORT->POM1 |= (1 << 1); /* P11 is N-ch open-drain output mode */ \
PORT->PMC1 &= ~(1 << 1); /* P11 is digital function */ \
}while(0)
/* ================================================================================================================== */
/* ================ SCI1 ================ */
/* ================================================================================================================== */
/* PIOR01 : TXD2 RXD2
* 0 P13 P14
* 1 P77 P76
*/
/**
* @brief UART2 Port Setting（Alternative to 2 group ports for 64pin product)
*/
#if 1
/* ToDo: You can allocate the TXD2 to P13 or P77 with PIOR01 register */
#define TXD2_PORT_SETTING() do{ \
PORT->PIOR0 &= ~(1 << 1); /* allocate TXD2 to P13 */ \
PORT->P1 |= (1 << 3); /* P13 output high level */ \
PORT->PM1 &= ~(1 << 3); /* P13 is used as TXD2 output */ \
PORT->POM1 &= ~(1 << 3); /* P13 is push-pull output mode */ \
PORT->PMC1 &= ~(1 << 3); /* P13 is digital function */ \
}while(0)
/* ToDo: You can allocate the RXD2 to P14 or P76 with PIOR01 register */
#define RXD2_PORT_SETTING() do{ \
PORT->PIOR0 &= ~(1 << 1); /* allocate RXD2 to P14 */ \
PORT->PM1 |= (1 << 4); /* P14 is used as RXD2 input */ \
PORT->PMC1 &= ~(1 << 4); /* P14 is digital function */ \
}while(0)
#else
/* ToDo: You can allocate the TXD2 to P13 or P77 with PIOR01 register */
#define TXD2_PORT_SETTING() do{ \
PORT->PIOR0 |= (1 << 1); /* allocate TXD2 to P77 */ \
PORT->P7 |= (1 << 7); /* P77 output high level */ \
PORT->PM7 &= ~(1 << 7); /* P77 is used as TXD2 output */ \
PORT->POM7 &= ~(1 << 7); /* P77 is push-pull output mode */ \
}while(0)
/* ToDo: You can allocate the RXD2 to P14 or P76 with PIOR01 register */
#define RXD2_PORT_SETTING() do{ \
PORT->PIOR0 |= (1 << 1); /* allocate RXD2 to P76 */ \
PORT->PM7 |= (1 << 4); /* P76 is used as RXD2 input */ \
}while(0)
#endif
/**
* @brief SPI20 Port Setting（Alternative to fixed port)
*/
/* ToDo: You can allocate the SS20 to any desired pins */
#define SS20_PORT_SETTING() do{ \
PORT->P6 |= (1 << 3); /* P63 output high level */ \
PORT->PM6 &= ~(1 << 3); /* P63 is used as SS20 output */ \
}while(0)
/* ToDo: You can allocate the SS20 to any desired pins */
#define SS20_PORT_SET() do{ \
PORT->P6 |= (1 << 3); /* P63 output high level */ \
}while(0)
/* ToDo: You can allocate the SS20 to any desired pins */
#define SS20_PORT_CLR() do{ \
PORT->P6 &= ~(1 << 3); /* P63 output low level */ \
}while(0)
#define SCLKI20_PORT_SETTING() do{ \
PORT->PIOR0 &= ~(1 << 1); /* allocate SCLK20 to P15 */ \
PORT->PM1 |= (1 << 5); /* P15 is used as SCLK20 input */ \
}while(0)
#define SCLKO20_PORT_SETTING() do{ \
PORT->PIOR0 &= ~(1 << 1); /* allocate SCLK20 to P15 */ \
PORT->P1 |= (1 << 5); /* P15 output high level */ \
PORT->PM1 &= ~(1 << 5); /* P15 is used as SCLK20 output */ \
PORT->POM1 &= ~(1 << 5); /* P15 is push-pull output mode */ \
}while(0)
#define SDO20_PORT_SETTING() do{ \
PORT->PIOR0 &= ~(1 << 1); /* allocate SDO20 to P15 */ \
PORT->P1 |= (1 << 3); /* P13 output high level */ \
PORT->PM1 &= ~(1 << 3); /* P13 is used as SDO20 output */ \
PORT->POM1 &= ~(1 << 3); /* P13 is push-pull output mode */ \
}while(0)
#define SDI20_PORT_SETTING() do{ \
PORT->PIOR0 &= ~(1 << 1); /* allocate SDI20 to P14 */ \
PORT->PM1 |= (1 << 4); /* P14 is used as SDI20 input */ \
}while(0)
/**
* @brief IIC20 Port Setting（Alternative to fixed port)
*/
#define SCL20_PORT_SETTING() do{ \
PORT->PIOR0 &= ~(1 << 1); /* allocate SCL20 to P15 */ \
PORT->P1 |= (1 << 5); /* P15 output high level */ \
PORT->PM1 &= ~(1 << 5); /* P15 is used as SCL20 output */ \
PORT->POM1 |= (1 << 5); /* P15 is N-ch open-drain output mode */ \
}while(0)
#define SDA20_PORT_SETTING() do{ \
PORT->PIOR0 &= ~(1 << 1); /* allocate SDA20 to P14 */ \
PORT->P1 |= (1 << 4); /* P14 output high level */ \
PORT->PM1 &= ~(1 << 4); /* P14 is used as SDA20 inout */ \
PORT->POM1 |= (1 << 4); /* P14 is N-ch open-drain output mode */ \
}while(0)
/**
* @brief SPI21 Port Setting (Alternative to fixed port)
*/
/* ToDo: You can allocate the SS21 to any desired pins */
#define SS21_PORT_SETTING() do{ \
PORT->P6 |= (1 << 3); /* P63 output high level */ \
PORT->PM6 &= ~(1 << 3); /* P63 is used as SS21 output */ \
}while(0)
/* ToDo: You can allocate the SS21 to any desired pins */
#define SS21_PORT_SET() do{ \
PORT->P6 |= (1 << 3); /* P63 output high level */ \
}while(0)
/* ToDo: You can allocate the SS21 to any desired pins */
#define SS21_PORT_CLR() do{ \
PORT->P6 &= ~(1 << 3); /* P63 output low level */ \
}while(0)
#define SCLKI21_PORT_SETTING() do{ \
PORT->PM7 |= (1 << 0); /* P70 is used as SCLK21 input */ \
}while(0)
#define SCLKO21_PORT_SETTING() do{ \
PORT->P7 |= (1 << 0); /* P70 output high level */ \
PORT->PM7 &= ~(1 << 0); /* P70 is used as SCLK21 output */ \
}while(0)
#define SDO21_PORT_SETTING() do{ \
PORT->P7 |= (1 << 2); /* P72 output high level */ \
PORT->PM7 &= ~(1 << 2); /* P72 is used as SDO21 output */ \
}while(0)
#define SDI21_PORT_SETTING() do{ \
PORT->PM7 |= (1 << 1); /* P71 is used as SDI21 input */ \
}while(0)
/**
* @brief IIC21 Port Setting (Alternative to fixed port)
*/
#define SCL21_PORT_SETTING() do{ \
PORT->P7 |= (1 << 0); /* P70 output high level */ \
PORT->PM7 &= ~(1 << 0); /* P70 is used as SCL21 output */ \
}while(0)
#define SDA21_PORT_SETTING() do{ \
PORT->P7 |= (1 << 1); /* P71 output high level */ \
PORT->PM7 &= ~(1 << 1); /* P71 is used as SDA21 inout */ \
PORT->POM7 |= (1 << 1); /* P71 is N-ch open-drain output mode */ \
}while(0)
/* ================================================================================================================== */
/* ================ SCI2 ================ */
/* ================================================================================================================== */
/*
*/
/**
* @brief UART3 Port Setting（Alternative to fixed port)
*/
#define TXD3_PORT_SETTING() do{ \
PORT->P14 |= (1 << 4); /* P144 output high level */ \
PORT->PM14 &= ~(1 << 4); /* P144 is used as TXD3 output */ \
PORT->POM14 &= ~(1 << 4); /* P144 is push-pull output mode */ \
PORT->PMC14 &= ~(1 << 4); /* P144 is digital function */ \
}while(0)
#define RXD3_PORT_SETTING() do{ \
PORT->PM14 |= (1 << 3); /* P143 is used as RXD3 input */ \
PORT->PMC14 &= ~(1 << 3); /* P143 is digital function */ \
}while(0)
/**
* @brief SPI30 Port Setting（Alternative to fixed port)
*/
/* ToDo: You can allocate the SS30 to any desired pins */
#define SS30_PORT_SETTING() do{ \
PORT->P15 |= (1 << 0); /* P150 output high level */ \
PORT->PM15 &= ~(1 << 0); /* P150 is used as SS30 output */ \
}while(0)
/* ToDo: You can allocate the SS30 to any desired pins */
#define SS30_PORT_SET() do{ \
PORT->P15 |= (1 << 0); /* P150 output high level */ \
}while(0)
/* ToDo: You can allocate the SS30 to any desired pins */
#define SS30_PORT_CLR() do{ \
PORT->P15 &= ~(1 << 0); /* P150 output low level */ \
}while(0)
#define SCLKI30_PORT_SETTING() do{ \
PORT->PM14 |= (1 << 2); /* P142 is used as SCLK30 input */ \
}while(0)
#define SCLKO30_PORT_SETTING() do{ \
PORT->P14 |= (1 << 2); /* P142 output high level */ \
PORT->PM14 &= ~(1 << 2); /* P142 is used as SCLK30 output */ \
PORT->POM14 &= ~(1 << 2); /* P142 is push-pull output mode */ \
}while(0)
#define SDO30_PORT_SETTING() do{ \
PORT->P14 |= (1 << 4); /* P144 output high level */ \
PORT->PM14 &= ~(1 << 4); /* P144 is used as SDO30 output */ \
PORT->POM14 &= ~(1 << 4); /* P144 is push-pull output mode */ \
}while(0)
#define SDI30_PORT_SETTING() do{ \
PORT->PM14 |= (1 << 3); /* P143 is used as SDI30 input */ \
}while(0)
/**
* @brief IIC30 Port Setting（Alternative to fixed port)
*/
#define SCL30_PORT_SETTING() do{ \
PORT->P14 |= (1 << 2); /* P142 output high level */ \
PORT->PM14 &= ~(1 << 2); /* P142 is used as SCL20 output */ \
PORT->POM14 |= (1 << 2); /* P142 is N-ch open-drain output mode */ \
}while(0)
#define SDA30_PORT_SETTING() do{ \
PORT->P14 |= (1 << 3); /* P143 output high level */ \
PORT->PM14 &= ~(1 << 3); /* P143 is used as SDA20 inout */ \
PORT->POM14 |= (1 << 3); /* P143 is N-ch open-drain output mode */ \
}while(0)
/**
* @brief SPI31 Port Setting (Alternative to fixed port)
*/
/* ToDo: You can allocate the SS31 to any desired pins */
#define SS31_PORT_SETTING() do{ \
PORT->P4 |= (1 << 2); /* P42 output high level */ \
PORT->PM4 &= ~(1 << 2); /* P42 is used as SS31 output */ \
}while(0)
/* ToDo: You can allocate the SS31 to any desired pins */
#define SS31_PORT_SET() do{ \
PORT->P4 |= (1 << 2); /* P42 output high level */ \
}while(0)
/* ToDo: You can allocate the SS31 to any desired pins */
#define SS31_PORT_CLR() do{ \
PORT->P4 &= ~(1 << 2); /* P42 output low level */ \
}while(0)
#define SCLKI31_PORT_SETTING() do{ \
PORT->PM4 |= (1 << 3); /* P43 is used as SCLK31 input */ \
}while(0)
#define SCLKO31_PORT_SETTING() do{ \
PORT->P4 |= (1 << 3); /* P43 output high level */ \
PORT->PM4 &= ~(1 << 3); /* P43 is used as SCLK31 output */ \
}while(0)
#define SDO31_PORT_SETTING() do{ \
PORT->P4 |= (1 << 5); /* P45 output high level */ \
PORT->PM4 &= ~(1 << 5); /* P45 is used as SDO31 output */ \
}while(0)
#define SDI31_PORT_SETTING() do{ \
PORT->PM4 |= (1 << 4); /* P44 is used as SDI31 input */ \
}while(0)
/**
* @brief IIC31 Port Setting (Alternative to fixed port)
*/
#define SCL31_PORT_SETTING() do{ \
PORT->P4 |= (1 << 3); /* P43 output high level */ \
PORT->PM4 &= ~(1 << 3); /* P43 is used as SCL31 output */ \
}while(0)
#define SDA31_PORT_SETTING() do{ \
PORT->P4 |= (1 << 4); /* P44 output high level */ \
PORT->PM4 &= ~(1 << 4); /* P44 is used as SDA31 inout */ \
PORT->POM4 |= (1 << 4); /* P44 is N-ch open-drain output mode */ \
}while(0)
/* ================================================================================================================== */
/* ================ IICA0 ================ */
/* ================================================================================================================== */
/**
* @brief IICA0 Port Setting（Alternative to 2 group ports)
*/
#if 1
/* ToDo: You can allocate the SCLA0 to P60 or P14 with PIOR02 register */
#define SCLA0_PORT_SETTING() do{ \
PORT->PIOR0 &= ~(1 << 2); /* allocate SCLA0 to P60 */ \
PORT->P6 &= ~(1 << 0); /* P60 output low level */ \
PORT->PM6 &= ~(1 << 0); /* P60 is used as SCLA0 output */ \
}while(0)
/* ToDo: You can allocate the SDAA0 to P61 or P15 with PIOR02 register */
#define SDAA0_PORT_SETTING() do{ \
PORT->PIOR0 &= ~(1 << 2); /* allocate SDAA0 to P61 */ \
PORT->P6 &= ~(1 << 1); /* P61 output low level */ \
PORT->PM6 &= ~(1 << 1); /* P61 is used as SDAA0 inout */ \
}while(0)
#else
/* ToDo: You can allocate the SCLA0 to P60 or P14 with PIOR02 register */
#define SCLA0_PORT_SETTING() do{ \
PORT->PIOR0 |= (1 << 2); /* allocate SCLA0 to P14 */ \
PORT->P1 &= ~(1 << 4); /* P14 output low level */ \
PORT->PM1 &= ~(1 << 4); /* P14 is used as SCLA0 output */ \
PORT->POM1 |= (1 << 4); /* P14 is N-ch open-drain output mode */ \
}while(0)
/* ToDo: You can allocate the SDAA0 to P61 or P15 with PIOR02 register */
#define SDAA0_PORT_SETTING() do{ \
PORT->PIOR0 |= (1 << 2); /* allocate SDAA0 to P15 */ \
PORT->P1 &= ~(1 << 5); /* P15 output low level */ \
PORT->PM1 &= ~(1 << 5); /* P15 is used as SDAA0 inout */ \
PORT->POM1 |= (1 << 5); /* P15 is N-ch open-drain output mode */ \
}while(0)
#endif
/* ================================================================================================================== */
/* ================ IICA1 ================ */
/* ================================================================================================================== */
/**
* @brief IICA1 Port Setting（Alternative to fixed port)
*/
#define SCLA1_PORT_SETTING() do{ \
PORT->P6 &= ~(1 << 2); /* P62 output low level */ \
PORT->PM6 &= ~(1 << 2); /* P62 is used as SCLA1 output */ \
}while(0)
#define SDAA1_PORT_SETTING() do{ \
PORT->P6 &= ~(1 << 3); /* P63 output low level */ \
PORT->PM6 &= ~(1 << 3); /* P63 is used as SDAA1 inout */ \
}while(0)
/* ================================================================================================================== */
/* ================ CAN0 ================ */
/* ================================================================================================================== */
/**
* @brief CAN0 Port Setting（Alternative to 2 group ports)
*/
#if 1
/* ToDo: You can allocate the CTXD0 to P02 or P51 with PIOR33 register */
#define CTXD0_PORT_SETTING() do{ \
PORT->PIOR3 &= ~(1 << 3); /* allocate CTXD0 to P02 */ \
PORT->P0 |= (1 << 2); /* P02 output high level */ \
PORT->PM0 &= ~(1 << 2); /* P02 is used as CTXD0 output */ \
PORT->PMC0 &= ~(1 << 2); /* P02 is digital function */ \
}while(0)
/* ToDo: You can allocate the CRXD0 to P03 or P50 with PIOR33 register */
#define CRXD0_PORT_SETTING() do{ \
PORT->PIOR3 &= ~(1 << 3); /* allocate CRXD0 to P03 */ \
PORT->PM0 |= (1 << 3); /* P03 is used as CRXD0 input */ \
PORT->PMC0 &= ~(1 << 3); /* P03 is digital function */ \
}while(0)
#else
/* ToDo: You can allocate the CTXD0 to P02 or P51 with PIOR33 register */
#define CTXD0_PORT_SETTING() do{ \
PORT->PIOR3 |= (1 << 3); /* allocate CTXD0 to P51 */ \
PORT->P5 |= (1 << 1); /* P51 output high level */ \
PORT->PM5 &= ~(1 << 1); /* P51 is used as CTXD0 output */ \
}while(0)
/* ToDo: You can allocate the CRXD0 to P03 or P50 with PIOR33 register */
#define CRXD0_PORT_SETTING() do{ \
PORT->PIOR3 |= (1 << 3); /* allocate CRXD0 to P50 */ \
PORT->PM5 |= (1 << 0); /* P50 is used as CRXD0 input */ \
}while(0)
#endif
/* ================================================================================================================== */
/* ================ CAN1 ================ */
/* ================================================================================================================== */
/**
* @brief CAN1 Port Setting（Alternative to fixed port)
*/
#define CTXD1_PORT_SETTING() do{ \
PORT->P6 |= (1 << 4); /* P64 output high level */ \
PORT->PM6 &= ~(1 << 4); /* P64 is used as CTXD1 output */ \
}while(0)
#define CRXD1_PORT_SETTING() do{ \
PORT->PM6 |= (1 << 5); /* P65 is used as CRXD1 input */ \
}while(0)
/* ================================================================================================================== */
/* ================ INTP ================ */
/* ================================================================================================================== */
/**
* @brief INTP Port Setting
*/
#define INTP0_PORT_SETTING() do{ \
PORT->PM13 |= (1 << 6); /* P136 is used as INTP0 input */ \
}while(0)
/* ToDo: You can allocate the INTP1 to P50 or P52 with PIOR00 register */
#define INTP1_PORT_SETTING() do{ \
PORT->PIOR0 &= ~(1 << 0); /* allocate INTP1 to P50 */ \
PORT->PM5 |= (1 << 0); /* P50 is used as INTP1 input */ \
}while(0)
/* ToDo: You can allocate the INTP2 to P51 or P53 with PIOR00 register */
#define INTP2_PORT_SETTING() do{ \
PORT->PIOR0 &= ~(1 << 0); /* allocate INTP2 to P51 */ \
PORT->PM5 |= (1 << 1); /* P51 is used as INTP2 input */ \
}while(0)
/* ToDo: You can allocate the INTP3 to P30 or P54 with PIOR00 register */
#define INTP3_PORT_SETTING() do{ \
PORT->PIOR0 &= ~(1 << 0); /* allocate INTP3 to P30 */ \
PORT->PM3 |= (1 << 0); /* P30 is used as INTP3 input */ \
}while(0)
/* ToDo: You can allocate the INTP4 to P31 or P55 with PIOR00 register */
#define INTP4_PORT_SETTING() do{ \
PORT->PIOR0 &= ~(1 << 0); /* allocate INTP4 to P31 */ \
PORT->PM3 |= (1 << 1); /* P31 is used as INTP4 input */ \
}while(0)
/* ToDo: You can allocate the INTP5 to P16 or P12 with PIOR04 register */
#define INTP5_PORT_SETTING() do{ \
PORT->PIOR0 &= ~(1 << 4); /* allocate INTP5 to P16 */ \
PORT->PM1 |= (1 << 6); /* P16 is used as INTP5 input */ \
}while(0)
#define INTP6_PORT_SETTING() do{ \
PORT->PM14 |= (1 << 0); /* P140 is used as INTP6 input */ \
}while(0)
#define INTP7_PORT_SETTING() do{ \
PORT->PM14 |= (1 << 1); /* P141 is used as INTP7 input */ \
}while(0)
/* ToDo: You can allocate the INTP8 to P74 or P42 with PIOR00 register */
#define INTP8_PORT_SETTING() do{ \
PORT->PIOR0 &= ~(1 << 0); /* allocate INTP8 to P74 */ \
PORT->PM7 |= (1 << 4); /* P74 is used as INTP8 input */ \
}while(0)
/* ToDo: You can allocate the INTP9 to P75 or P43 with PIOR00 register */
#define INTP9_PORT_SETTING() do{ \
PORT->PIOR0 &= ~(1 << 0); /* allocate INTP9 to P75 */ \
PORT->PM7 |= (1 << 5); /* P75 is used as INTP9 input */ \
}while(0)
/* ToDo: You can allocate the INTP10 to P76 or P05 with PIOR01 register */
#define INTP10_PORT_SETTING() do{ \
PORT->PIOR0 &= ~(1 << 0); /* allocate INTP10 to P76 */ \
PORT->PM7 |= (1 << 6); /* P76 is used as INTP10 input */ \
}while(0)
/* ToDo: You can allocate the INTP11 to P77 or P06 with PIOR01 register */
#define INTP11_PORT_SETTING() do{ \
PORT->PIOR0 &= ~(1 << 0); /* allocate INTP11 to P77 */ \
PORT->PM7 |= (1 << 7); /* P77 is used as INTP11 input */ \
}while(0)
/** @} */ /* End of group Peripherals_Port_Setting_Definations */
#endif
Firmware/Project/Cmsemicon/BAT32A279/MDK_ARM/RTE/Device/BAT32A239KK80FA/isr_BAT32A239.c deleted 100644 → 0
View file @ 6e32a063
///***********************************************************************************************************************
//* Copyright (C) All rights reserved.
//***********************************************************************************************************************/
///***********************************************************************************************************************
//* @file isr.c
//* @brief This file implements device driver for interrupt module.
//* @version 1.0.0
//* @date 2021/06/03
//***********************************************************************************************************************/
///***********************************************************************************************************************
//Includes
//***********************************************************************************************************************/
//#include "userdefine.h"
//#include "BAT32A239.h"
///***********************************************************************************************************************
//Pragma directive
//***********************************************************************************************************************/
///***********************************************************************************************************************
//Global variables and functions
//***********************************************************************************************************************/
///***********************************************************IRQ00_Handler************************************************************/
//__WEAK void lvi_interrupt(void)
//{
// INTC_ClearPendingIRQ(LVI_IRQn);
//}
//__WEAK void osdc_interrupt(void)
//{
// INTC_ClearPendingIRQ(OSDC_IRQn);
//}
//__WEAK void ocrv_interrupt(void)
//{
// INTC_ClearPendingIRQ(OCRV_IRQn);
//}
//void IRQ00_Handler(void)
//{
// if(INTC_GetPendingIRQ(LVI_IRQn))
// {
// lvi_interrupt();
// }
//
// if(INTC_GetPendingIRQ(OSDC_IRQn))
// {
// osdc_interrupt();
// }
//
// if(INTC_GetPendingIRQ(OCRV_IRQn))
// {
// ocrv_interrupt();
// }
//}
///***********************************************************IRQ01_Handler************************************************************/
//__WEAK void intp0_interrupt(void)
//{
// INTC_ClearPendingIRQ(INTP0_IRQn);
//}
//__WEAK void intp6_interrupt(void)
//{
// INTC_ClearPendingIRQ(INTP6_IRQn);
//}
//void IRQ01_Handler(void)
//{
// if(INTC_GetPendingIRQ(INTP0_IRQn))
// {
// intp0_interrupt();
// }
//
// if(INTC_GetPendingIRQ(INTP6_IRQn))
// {
// intp6_interrupt();
// }
//
//}
///***********************************************************IRQ02_Handler************************************************************/
//__WEAK void intp1_interrupt(void)
//{
// INTC_ClearPendingIRQ(INTP1_IRQn);
//}
//__WEAK void intp7_interrupt(void)
//{
// INTC_ClearPendingIRQ(INTP7_IRQn);
//}
//void IRQ02_Handler(void)
//{
// if(INTC_GetPendingIRQ(INTP1_IRQn))
// {
// intp1_interrupt();
// }
//
// if(INTC_GetPendingIRQ(INTP7_IRQn))
// {
// intp7_interrupt();
// }
//
//}
///***********************************************************IRQ03_Handler************************************************************/
//__WEAK void intp2_interrupt(void)
//{
// INTC_ClearPendingIRQ(INTP2_IRQn);
//}
//__WEAK void intp8_interrupt(void)
//{
// INTC_ClearPendingIRQ(INTP8_IRQn);
//}
//void IRQ03_Handler(void)
//{
// if(INTC_GetPendingIRQ(INTP2_IRQn))
// {
// intp2_interrupt();
// }
//
// if(INTC_GetPendingIRQ(INTP8_IRQn))
// {
// intp8_interrupt();
// }
//
//}
///***********************************************************IRQ04_Handler************************************************************/
//__WEAK void intp3_interrupt(void)
//{
// INTC_ClearPendingIRQ(INTP3_IRQn);
//}
//__WEAK void intp9_interrupt(void)
//{
// INTC_ClearPendingIRQ(INTP9_IRQn);
//}
//void IRQ04_Handler(void)
//{
// if(INTC_GetPendingIRQ(INTP3_IRQn))
// {
// intp3_interrupt();
// }
//
// if(INTC_GetPendingIRQ(INTP9_IRQn))
// {
// intp9_interrupt();
// }
//
//}
///***********************************************************IRQ05_Handler************************************************************/
//__WEAK void intp4_interrupt(void)
//{
// INTC_ClearPendingIRQ(INTP4_IRQn);
//}
//__WEAK void intp10_interrupt(void)
//{
// INTC_ClearPendingIRQ(INTP10_IRQn);
//}
//void IRQ05_Handler(void)
//{
// if(INTC_GetPendingIRQ(INTP4_IRQn))
// {
// intp4_interrupt();
// }
//
// if(INTC_GetPendingIRQ(INTP10_IRQn))
// {
// intp10_interrupt();
// }
//
//}
///***********************************************************IRQ06_Handler************************************************************/
//__WEAK void intp5_interrupt(void)
//{
// INTC_ClearPendingIRQ(INTP5_IRQn);
//}
//__WEAK void intp11_interrupt(void)
//{
// INTC_ClearPendingIRQ(INTP11_IRQn);
//}
//void IRQ06_Handler(void)
//{
// if(INTC_GetPendingIRQ(INTP5_IRQn))
// {
// intp5_interrupt();
// }
//
// if(INTC_GetPendingIRQ(INTP11_IRQn))
// {
// intp11_interrupt();
// }
//
//}
///***********************************************************IRQ07_Handler************************************************************/
//__WEAK void uart2_interrupt_send(void)
//{
// INTC_ClearPendingIRQ(ST2_IRQn);
//}
//__WEAK void spi20_interrupt(void)
//{
// INTC_ClearPendingIRQ(SPI20_IRQn);
//}
//__WEAK void iic20_interrupt(void)
//{
// INTC_ClearPendingIRQ(IIC20_IRQn);
//}
//__WEAK void uart3_interrupt_send(void)
//{
// INTC_ClearPendingIRQ(ST3_IRQn);
//}
//__WEAK void spi30_interrupt(void)
//{
// INTC_ClearPendingIRQ(SPI30_IRQn);
//}
//__WEAK void iic30_interrupt(void)
//{
// INTC_ClearPendingIRQ(IIC30_IRQn);
//}
//void IRQ07_Handler(void)
//{
//#if defined(USE_SCI_UART2_TX)
// if(INTC_GetPendingIRQ(ST2_IRQn))
// {
// uart2_interrupt_send();
// }
//#elif defined(USE_SCI_SPI20)
// if(INTC_GetPendingIRQ(SPI20_IRQn))
// {
// spi20_interrupt();
// }
//#elif defined(USE_SCI_IIC20)
// if(INTC_GetPendingIRQ(IIC20_IRQn))
// {
// iic20_interrupt();
// }
//#endif
//#if defined(USE_SCI_UART3_TX)
// if(INTC_GetPendingIRQ(ST3_IRQn))
// {
// uart3_interrupt_send();
// }
//#elif defined(USE_SCI_SPI30)
// if(INTC_GetPendingIRQ(SPI30_IRQn))
// {
// spi30_interrupt();
// }
//#elif defined(USE_SCI_IIC30)
// if(INTC_GetPendingIRQ(IIC30_IRQn))
// {
// iic30_interrupt();
// }
//#endif
//}
///***********************************************************IRQ08_Handler************************************************************/
//__WEAK void uart2_interrupt_receive(void)
//{
// INTC_ClearPendingIRQ(SR2_IRQn);
//}
//__WEAK void spi21_interrupt(void)
//{
// INTC_ClearPendingIRQ(SPI21_IRQn);
//}
//__WEAK void iic21_interrupt(void)
//{
// INTC_ClearPendingIRQ(IIC21_IRQn);
//}
//__WEAK void uart3_interrupt_receive(void)
//{
// INTC_ClearPendingIRQ(SR3_IRQn);
//}
//__WEAK void spi31_interrupt(void)
//{
// INTC_ClearPendingIRQ(SPI31_IRQn);
//}
//__WEAK void iic31_interrupt(void)
//{
// INTC_ClearPendingIRQ(IIC31_IRQn);
//}
//void IRQ08_Handler(void)
//{
//#if defined(USE_SCI_UART2_RX)
// if(INTC_GetPendingIRQ(SR2_IRQn))
// {
// uart2_interrupt_receive();
// }
//#elif defined(USE_SCI_SPI21)
// if(INTC_GetPendingIRQ(SPI21_IRQn))
// {
// spi21_interrupt();
// }
//#elif defined(USE_SCI_IIC21)
// if(INTC_GetPendingIRQ(IIC21_IRQn))
// {
// iic21_interrupt();
// }
//#endif
//#if defined(USE_SCI_UART3_RX)
// if(INTC_GetPendingIRQ(SR3_IRQn))
// {
// uart3_interrupt_receive();
// }
//#elif defined(USE_SCI_SPI31)
// if(INTC_GetPendingIRQ(SPI31_IRQn))
// {
// spi31_interrupt();
// }
//#elif defined(USE_SCI_IIC31)
// if(INTC_GetPendingIRQ(IIC31_IRQn))
// {
// iic31_interrupt();
// }
//#endif
//}
///***********************************************************IRQ09_Handler************************************************************/
//__WEAK void sre2_interrupt(void)
//{
// INTC_ClearPendingIRQ(SRE2_IRQn);
//}
//__WEAK void CAN0Err_Interrupt(void)
//{
// INTC_ClearPendingIRQ(CAN0ERR_IRQn);
//}
//void IRQ09_Handler(void)
//{
// if(INTC_GetPendingIRQ(SRE2_IRQn))
// {
// sre2_interrupt();
// }
//
// if(INTC_GetPendingIRQ(CAN0ERR_IRQn))
// {
// CAN0Err_Interrupt();
// }
//
//}
///***********************************************************IRQ10_Handler************************************************************/
//__WEAK void uart0_interrupt_send(void)
//{
// INTC_ClearPendingIRQ(ST0_IRQn);
//}
//__WEAK void spi00_interrupt(void)
//{
// INTC_ClearPendingIRQ(SPI00_IRQn);
//}
//__WEAK void iic00_interrupt(void)
//{
// INTC_ClearPendingIRQ(IIC00_IRQn);
//}
//void IRQ10_Handler(void)
//{
//#if defined(USE_SCI_UART0_TX)
// if(INTC_GetPendingIRQ(ST0_IRQn))
// {
// uart0_interrupt_send();
// }
//#elif defined(USE_SCI_SPI00)
// if(INTC_GetPendingIRQ(SPI00_IRQn))
// {
// spi00_interrupt();
// }
//#elif defined(USE_SCI_IIC00)
// if(INTC_GetPendingIRQ(IIC00_IRQn))
// {
// iic00_interrupt();
// }
//#endif
//}
///***********************************************************IRQ11_Handler************************************************************/
//__WEAK void uart0_interrupt_receive(void)
//{
// INTC_ClearPendingIRQ(SR0_IRQn);
//}
//__WEAK void spi01_interrupt(void)
//{
// INTC_ClearPendingIRQ(SPI01_IRQn);
//}
//__WEAK void iic01_interrupt(void)
//{
// INTC_ClearPendingIRQ(IIC01_IRQn);
//}
//void IRQ11_Handler(void)
//{
//#if defined(USE_SCI_UART0_RX)
// if(INTC_GetPendingIRQ(SR0_IRQn))
// {
// uart0_interrupt_receive();
// }
//#elif defined(USE_SCI_SPI01)
// if(INTC_GetPendingIRQ(SPI01_IRQn))
// {
// spi01_interrupt();
// }
//#elif defined(USE_SCI_IIC01)
// if(INTC_GetPendingIRQ(IIC01_IRQn))
// {
// iic01_interrupt();
// }
//#endif
//}
///***********************************************************IRQ12_Handler************************************************************/
//__WEAK void sre0_interrupt(void)
//{
// INTC_ClearPendingIRQ(SRE0_IRQn);
//}
//__WEAK void tm01h_interrupt(void)
//{
// INTC_ClearPendingIRQ(TM01H_IRQn);
//}
//void IRQ12_Handler(void)
//{
// if(INTC_GetPendingIRQ(SRE0_IRQn))
// {
// sre0_interrupt();
// }
//
// if(INTC_GetPendingIRQ(TM01H_IRQn))
// {
// tm01h_interrupt();
// }
//
//}
///***********************************************************IRQ13_Handler************************************************************/
//__WEAK void uart1_interrupt_send(void)
//{
// INTC_ClearPendingIRQ(ST1_IRQn);
//}
//__WEAK void spi10_interrupt(void)
//{
// INTC_ClearPendingIRQ(SPI10_IRQn);
//}
//__WEAK void iic10_interrupt(void)
//{
// INTC_ClearPendingIRQ(IIC10_IRQn);
//}
//void IRQ13_Handler(void)
//{
//#if defined(USE_SCI_UART1_TX)
// if(INTC_GetPendingIRQ(ST1_IRQn))
// {
// uart1_interrupt_send();
// }
//#elif defined(USE_SCI_SPI10)
// if(INTC_GetPendingIRQ(SPI10_IRQn))
// {
// spi10_interrupt();
// }
//#elif defined(USE_SCI_IIC10)
// if(INTC_GetPendingIRQ(IIC10_IRQn))
// {
// iic10_interrupt();
// }
//#endif
//}
///***********************************************************IRQ14_Handler************************************************************/
//__WEAK void uart1_interrupt_receive(void)
//{
// INTC_ClearPendingIRQ(SR1_IRQn);
//}
//__WEAK void spi11_interrupt(void)
//{
// INTC_ClearPendingIRQ(SPI11_IRQn);
//}
//__WEAK void iic11_interrupt(void)
//{
// INTC_ClearPendingIRQ(IIC11_IRQn);
//}
//void IRQ14_Handler(void)
//{
//#if defined(USE_SCI_UART1_RX)
// if(INTC_GetPendingIRQ(SR1_IRQn))
// {
// uart1_interrupt_receive();
// }
//#elif defined(USE_SCI_SPI11)
// if(INTC_GetPendingIRQ(SPI11_IRQn))
// {
// spi11_interrupt();
// }
//#elif defined(USE_SCI_IIC11)
// if(INTC_GetPendingIRQ(IIC11_IRQn))
// {
// iic11_interrupt();
// }
//#endif
//}
///***********************************************************IRQ15_Handler************************************************************/
//__WEAK void sre1_interrupt(void)
//{
// INTC_ClearPendingIRQ(SRE1_IRQn);
//}
//__WEAK void tm03h_interrupt(void)
//{
// INTC_ClearPendingIRQ(TM03H_IRQn);
//}
//void IRQ15_Handler(void)
//{
// if(INTC_GetPendingIRQ(SRE1_IRQn))
// {
// sre1_interrupt();
// }
//
// if(INTC_GetPendingIRQ(TM03H_IRQn))
// {
// tm03h_interrupt();
// }
//
//}
///***********************************************************IRQ16_Handler************************************************************/
//__WEAK void iica0_interrupt(void)
//{
// INTC_ClearPendingIRQ(IICA0_IRQn);
//}
//__WEAK void div_interrupt(void)
//{
// INTC_ClearPendingIRQ(DIV_IRQn);
//}
//__WEAK void iica1_interrupt(void)
//{
// INTC_ClearPendingIRQ(IICA1_IRQn);
//}
//void IRQ16_Handler(void)
//{
// if(INTC_GetPendingIRQ(IICA0_IRQn))
// {
// iica0_interrupt();
// }
//
// if(INTC_GetPendingIRQ(DIV_IRQn))
// {
// div_interrupt();
// }
//
// if(INTC_GetPendingIRQ(IICA1_IRQn))
// {
// iica1_interrupt();
// }
//
//}
///***********************************************************IRQ17_Handler************************************************************/
//__WEAK void tm40_channel0_interrupt(void)
//{
// INTC_ClearPendingIRQ(TM00_IRQn);
//}
//__WEAK void tm81_channel10_interrupt(void)
//{
// INTC_ClearPendingIRQ(TM10_IRQn);
//}
//__WEAK void tm81_channel14_interrupt(void)
//{
// INTC_ClearPendingIRQ(TM14_IRQn);
//}
//void IRQ17_Handler(void)
//{
// if(INTC_GetPendingIRQ(TM00_IRQn))
// {
// tm40_channel0_interrupt();
// }
//
// if(INTC_GetPendingIRQ(TM10_IRQn))
// {
// tm81_channel10_interrupt();
// }
//
// if(INTC_GetPendingIRQ(TM14_IRQn))
// {
// tm81_channel14_interrupt();
// }
//}
///***********************************************************IRQ18_Handler************************************************************/
//__WEAK void tm40_channel1_interrupt(void)
//{
// INTC_ClearPendingIRQ(TM01_IRQn);
//}
//__WEAK void tm81_channel11_interrupt(void)
//{
// INTC_ClearPendingIRQ(TM11_IRQn);
//}
//__WEAK void tm81_channel15_interrupt(void)
//{
// INTC_ClearPendingIRQ(TM15_IRQn);
//}
//void IRQ18_Handler(void)
//{
// if(INTC_GetPendingIRQ(TM01_IRQn))
// {
// tm40_channel1_interrupt();
// }
//
// if(INTC_GetPendingIRQ(TM11_IRQn))
// {
// tm81_channel11_interrupt();
// }
//
// if(INTC_GetPendingIRQ(TM15_IRQn))
// {
// tm81_channel15_interrupt();
// }
//}
///***********************************************************IRQ19_Handler************************************************************/
//__WEAK void tm40_channel2_interrupt(void)
//{
// INTC_ClearPendingIRQ(TM02_IRQn);
//}
//__WEAK void tm81_channel12_interrupt(void)
//{
// INTC_ClearPendingIRQ(TM12_IRQn);
//}
//__WEAK void tm81_channel16_interrupt(void)
//{
// INTC_ClearPendingIRQ(TM16_IRQn);
//}
//void IRQ19_Handler(void)
//{
// if(INTC_GetPendingIRQ(TM02_IRQn))
// {
// tm40_channel2_interrupt();
// }
//
// if(INTC_GetPendingIRQ(TM12_IRQn))
// {
// tm81_channel12_interrupt();
// }
//
// if(INTC_GetPendingIRQ(TM16_IRQn))
// {
// tm81_channel16_interrupt();
// }
//}
///***********************************************************IRQ20_Handler************************************************************/
//__WEAK void tm40_channel3_interrupt(void)
//{
// INTC_ClearPendingIRQ(TM03_IRQn);
//}
//__WEAK void tm81_channel13_interrupt(void)
//{
// INTC_ClearPendingIRQ(TM13_IRQn);
//}
//__WEAK void tm81_channel17_interrupt(void)
//{
// INTC_ClearPendingIRQ(TM17_IRQn);
//}
//void IRQ20_Handler(void)
//{
// if(INTC_GetPendingIRQ(TM03_IRQn))
// {
// tm40_channel3_interrupt();
// }
//
// if(INTC_GetPendingIRQ(TM13_IRQn))
// {
// tm81_channel13_interrupt();
// }
//
// if(INTC_GetPendingIRQ(TM17_IRQn))
// {
// tm81_channel17_interrupt();
// }
//}
///***********************************************************IRQ21_Handler************************************************************/
//__WEAK void adc_interrupt(void)
//{
// INTC_ClearPendingIRQ(ADC_IRQn);
//}
//void IRQ21_Handler(void)
//{
// if(INTC_GetPendingIRQ(ADC_IRQn))
// {
// adc_interrupt();
// }
//
//}
///***********************************************************IRQ22_Handler************************************************************/
//__WEAK void rtc_interrupt(void)
//{
// INTC_ClearPendingIRQ(RTC_IRQn);
//}
//__WEAK void it_interrupt(void)
//{
// INTC_ClearPendingIRQ(IT_IRQn);
//}
//void IRQ22_Handler(void)
//{
// if(INTC_GetPendingIRQ(RTC_IRQn))
// {
// rtc_interrupt();
// }
//
// if(INTC_GetPendingIRQ(IT_IRQn))
// {
// it_interrupt();
// }
//
//}
///***********************************************************IRQ23_Handler************************************************************/
//__WEAK void key_interrupt(void)
//{
// INTC_ClearPendingIRQ(KEY_IRQn);
//}
//__WEAK void CAN0Rec_Interrupt(void)
//{
// INTC_ClearPendingIRQ(CAN0REC_IRQn);
//}
//void IRQ23_Handler(void)
//{
// if(INTC_GetPendingIRQ(KEY_IRQn))
// {
// key_interrupt();
// }
//
// if(INTC_GetPendingIRQ(CAN0REC_IRQn))
// {
// CAN0Rec_Interrupt();
// }
//
//}
///***********************************************************IRQ24_Handler************************************************************/
//__WEAK void cmp0_interrupt(void)
//{
// INTC_ClearPendingIRQ(CMP0_IRQn);
//}
//__WEAK void CAN0Wup_Interrupt(void)
//{
// INTC_ClearPendingIRQ(CAN0WUP_IRQn);
//}
//void IRQ24_Handler(void)
//{
// if(INTC_GetPendingIRQ(CMP0_IRQn))
// {
// cmp0_interrupt();
// }
//
// if(INTC_GetPendingIRQ(CAN0WUP_IRQn))
// {
// CAN0Wup_Interrupt();
// }
//
//}
///***********************************************************IRQ25_Handler************************************************************/
//__WEAK void cmp1_interrupt(void)
//{
// INTC_ClearPendingIRQ(CMP1_IRQn);
//}
//__WEAK void CAN0Trx_Interrupt(void)
//{
// INTC_ClearPendingIRQ(CAN0TRX_IRQn);
//}
//void IRQ25_Handler(void)
//{
// if(INTC_GetPendingIRQ(CMP1_IRQn))
// {
// cmp1_interrupt();
// }
//
// if(INTC_GetPendingIRQ(CAN0TRX_IRQn))
// {
// CAN0Trx_Interrupt();
// }
//
//}
///***********************************************************IRQ26_Handler************************************************************/
//__WEAK void tma0_interrupt(void)
//{
// INTC_ClearPendingIRQ(TMA_IRQn);
//}
//__WEAK void CAN1Err_Interrupt(void)
//{
// INTC_ClearPendingIRQ(CAN1ERR_IRQn);
//}
//void IRQ26_Handler(void)
//{
// if(INTC_GetPendingIRQ(TMA_IRQn))
// {
// tma0_interrupt();
// }
//
// if(INTC_GetPendingIRQ(CAN1ERR_IRQn))
// {
// CAN1Err_Interrupt();
// }
//
//}
///***********************************************************IRQ27_Handler************************************************************/
//__WEAK void tmm0_interrupt(void)
//{
// INTC_ClearPendingIRQ(TMM0_IRQn);
//}
//void IRQ27_Handler(void)
//{
// if(INTC_GetPendingIRQ(TMM0_IRQn))
// {
// tmm0_interrupt();
// }
//
//}
///***********************************************************IRQ28_Handler************************************************************/
//__WEAK void tmm1_interrupt(void)
//{
// INTC_ClearPendingIRQ(TMM1_IRQn);
//}
//void IRQ28_Handler(void)
//{
// if(INTC_GetPendingIRQ(TMM1_IRQn))
// {
// tmm1_interrupt();
// }
//
//}
///***********************************************************IRQ29_Handler************************************************************/
//__WEAK void tmb0_interrupt(void)
//{
// INTC_ClearPendingIRQ(TMB_IRQn);
//}
//__WEAK void CAN1Rec_Interrupt(void)
//{
// INTC_ClearPendingIRQ(CAN1REC_IRQn);
//}
//void IRQ29_Handler(void)
//{
// if(INTC_GetPendingIRQ(TMB_IRQn))
// {
// tmb0_interrupt();
// }
//
// if(INTC_GetPendingIRQ(CAN1REC_IRQn))
// {
// CAN1Rec_Interrupt();
// }
//
//}
///***********************************************************IRQ30_Handler************************************************************/
//__WEAK void tmc_interrupt(void)
//{
// INTC_ClearPendingIRQ(TMC_IRQn);
//}
//__WEAK void CAN1Wup_Interrupt(void)
//{
// INTC_ClearPendingIRQ(CAN1WUP_IRQn);
//}
//void IRQ30_Handler(void)
//{
// if(INTC_GetPendingIRQ(TMC_IRQn))
// {
// tmc_interrupt();
// }
//
// if(INTC_GetPendingIRQ(CAN1WUP_IRQn))
// {
// CAN1Wup_Interrupt();
// }
//
//}
///***********************************************************IRQ31_Handler************************************************************/
//__WEAK void flash_interrupt(void)
//{
// INTC_ClearPendingIRQ(FMC_IRQn);
//}
//__WEAK void CAN1Trx_Interrupt(void)
//{
// INTC_ClearPendingIRQ(CAN1TRX_IRQn);
//}
//void IRQ31_Handler(void)
//{
// if(INTC_GetPendingIRQ(FMC_IRQn))
// {
// flash_interrupt();
// }
//
// if(INTC_GetPendingIRQ(CAN1TRX_IRQn))
// {
// CAN1Trx_Interrupt();
// }
//
//}
Firmware/Project/Cmsemicon/BAT32A279/MDK_ARM/RTE/Device/BAT32A239KK80FA/startup_BAT32A239.s deleted 100644 → 0
View file @ 6e32a063
;/**************************************************************************//**
; * @file startup_BAT32A239.s
; * @brief CMSIS Cortex-M ARMv6-M based Core Device Startup File for
; * Device BAT32A239
; * @version V1.00
; * @date 2019/04/24
; ******************************************************************************/
;/*
; * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
; *
; * SPDX-License-Identifier: Apache-2.0
; *
; * Licensed under the Apache License, Version 2.0 (the License); you may
; * not use this file except in compliance with the License.
; * You may obtain a copy of the License at
; *
; * www.apache.org/licenses/LICENSE-2.0
; *
; * Unless required by applicable law or agreed to in writing, software
; * distributed under the License is distributed on an AS IS BASIS, WITHOUT
; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
; * See the License for the specific language governing permissions and
; * limitations under the License.
; */
;/*
;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
;*/
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Stack_Size EQU 0x00000600
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Heap_Size EQU 0x00000100
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
; ToDo: Add here the vectors for the device specific external interrupts handler
DCD IRQ00_Handler ; LVI IRQ
DCD IRQ01_Handler ; INTP0 or INTP6 IRQ
DCD IRQ02_Handler ; INTP1 or INTP7 IRQ
DCD IRQ03_Handler ; INTP2 or INTP8 IRQ
DCD IRQ04_Handler ; INTP3 or INTP9 IRQ
DCD IRQ05_Handler ; INTP4 or INTP10 IRQ
DCD IRQ06_Handler ; INTP5 or INTP11 IRQ
DCD IRQ07_Handler ; ST2/SPI20/IIC20 IRQ
DCD IRQ08_Handler ; SR2/SPI21/IIC21 IRQ
DCD IRQ09_Handler ; SRE2 IRQ
DCD IRQ10_Handler ; ST0/SPI00/IIC00 IRQ
DCD IRQ11_Handler ; SR0/SPI01/IIC01 IRQ
DCD IRQ12_Handler ; SRE0 or TM01H IRQ
DCD IRQ13_Handler ; ST1/SPI10/IIC10 IRQ
DCD IRQ14_Handler ; SR1/SPI11/IIC11 IRQ
DCD IRQ15_Handler ; SRE1 or TM03H IRQ
DCD IRQ16_Handler ; IICA or DIV IRQ
DCD IRQ17_Handler ; TM00 IRQ
DCD IRQ18_Handler ; TM01 IRQ
DCD IRQ19_Handler ; TM02 IRQ
DCD IRQ20_Handler ; TM03 IRQ
DCD IRQ21_Handler ; ADC IRQ
DCD IRQ22_Handler ; RTC or IT IRQ
DCD IRQ23_Handler ; KEY IRQ
DCD IRQ24_Handler ; CMP0 IRQ
DCD IRQ25_Handler ; CMP1 IRQ
DCD IRQ26_Handler ; TMA IRQ
DCD IRQ27_Handler ; TMM0 IRQ
DCD IRQ28_Handler ; TMM1 IRQ
DCD IRQ29_Handler ; TMB IRQ
DCD IRQ30_Handler ; TMC IRQ
DCD IRQ31_Handler ; FMC IRQ
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset Handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT SystemInit
IMPORT __main
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler\
PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
MemManage_Handler\
PROC
EXPORT MemManage_Handler [WEAK]
B .
ENDP
BusFault_Handler\
PROC
EXPORT BusFault_Handler [WEAK]
B .
ENDP
UsageFault_Handler\
PROC
EXPORT UsageFault_Handler [WEAK]
B .
ENDP
SVC_Handler\
PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
DebugMon_Handler\
PROC
EXPORT DebugMon_Handler [WEAK]
B .
ENDP
PendSV_Handler\
PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler\
PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
IRQ00_Handler\
PROC
EXPORT IRQ00_Handler [WEAK]
B .
ENDP
IRQ01_Handler\
PROC
EXPORT IRQ01_Handler [WEAK]
B .
ENDP
IRQ02_Handler\
PROC
EXPORT IRQ02_Handler [WEAK]
B .
ENDP
IRQ03_Handler\
PROC
EXPORT IRQ03_Handler [WEAK]
B .
ENDP
IRQ04_Handler\
PROC
EXPORT IRQ04_Handler [WEAK]
B .
ENDP
IRQ05_Handler\
PROC
EXPORT IRQ05_Handler [WEAK]
B .
ENDP
IRQ06_Handler\
PROC
EXPORT IRQ06_Handler [WEAK]
B .
ENDP
IRQ07_Handler\
PROC
EXPORT IRQ07_Handler [WEAK]
B .
ENDP
IRQ08_Handler\
PROC
EXPORT IRQ08_Handler [WEAK]
B .
ENDP
IRQ09_Handler\
PROC
EXPORT IRQ09_Handler [WEAK]
B .
ENDP
IRQ10_Handler\
PROC
EXPORT IRQ10_Handler [WEAK]
B .
ENDP
IRQ11_Handler\
PROC
EXPORT IRQ11_Handler [WEAK]
B .
ENDP
IRQ12_Handler\
PROC
EXPORT IRQ12_Handler [WEAK]
B .
ENDP
IRQ13_Handler\
PROC
EXPORT IRQ13_Handler [WEAK]
B .
ENDP
IRQ14_Handler\
PROC
EXPORT IRQ14_Handler [WEAK]
B .
ENDP
IRQ15_Handler\
PROC
EXPORT IRQ15_Handler [WEAK]
B .
ENDP
IRQ16_Handler\
PROC
EXPORT IRQ16_Handler [WEAK]
B .
ENDP
IRQ17_Handler\
PROC
EXPORT IRQ17_Handler [WEAK]
B .
ENDP
IRQ18_Handler\
PROC
EXPORT IRQ18_Handler [WEAK]
B .
ENDP
IRQ19_Handler\
PROC
EXPORT IRQ19_Handler [WEAK]
B .
ENDP
IRQ20_Handler\
PROC
EXPORT IRQ20_Handler [WEAK]
B .
ENDP
IRQ21_Handler\
PROC
EXPORT IRQ21_Handler [WEAK]
B .
ENDP
IRQ22_Handler\
PROC
EXPORT IRQ22_Handler [WEAK]
B .
ENDP
IRQ23_Handler\
PROC
EXPORT IRQ23_Handler [WEAK]
B .
ENDP
IRQ24_Handler\
PROC
EXPORT IRQ24_Handler [WEAK]
B .
ENDP
IRQ25_Handler\
PROC
EXPORT IRQ25_Handler [WEAK]
B .
ENDP
IRQ26_Handler\
PROC
EXPORT IRQ26_Handler [WEAK]
B .
ENDP
IRQ27_Handler\
PROC
EXPORT IRQ27_Handler [WEAK]
B .
ENDP
IRQ28_Handler\
PROC
EXPORT IRQ28_Handler [WEAK]
B .
ENDP
IRQ29_Handler\
PROC
EXPORT IRQ29_Handler [WEAK]
B .
ENDP
IRQ30_Handler\
PROC
EXPORT IRQ30_Handler [WEAK]
B .
ENDP
IRQ31_Handler\
PROC
EXPORT IRQ31_Handler [WEAK]
B .
ENDP
ALIGN
; User Initial Stack & Heap
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap PROC
LDR R0, = Heap_Mem
LDR R1, =(Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ENDP
ALIGN
ENDIF
END
Firmware/Project/Cmsemicon/BAT32A279/MDK_ARM/RTE/Device/BAT32A239KK80FA/system_BAT32A239.c deleted 100644 → 0
View file @ 6e32a063
/**************************************************************************//**
* @file system_BAT32A239.c
* @brief CMSIS Cortex-M0+ Device Peripheral Access Layer Source File for
* Device BAT32A239
* @version V1.00
* @date 2019/04/24
******************************************************************************/
/*
* Copyright (c) 2009-2018 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include <stdint.h>
#include "BAT32A239.h"
/*----------------------------------------------------------------------------
Define clocks
*----------------------------------------------------------------------------*/
/* ToDo: add here your necessary defines for device initialization
following is an example for different system frequencies */
#define __HSI (64000000UL)
#define __XTAL (8000000UL) /* Oscillator frequency */
#define __SYS_OSC_CLK (___HSI) /* Main oscillator frequency */
#define __SYSTEM_CLOCK (64000000UL)
/** @addtogroup Configuration_of_User_Option_Byte
* @{
*/
typedef enum {
HOCO_FREQ_64MHZ = 0xF8, /*!< fHOCO = 64MHz, fIH = 64MHz */
HOCO_FREQ_48MHZ = 0xF0, /*!< fHOCO = 48MHz, fIH = 48MHz */
HOCO_FREQ_32MHZ = 0xE8, /*!< fHOCO = 32MHz, fIH = 32MHz */
HOCO_FREQ_24MHZ = 0xE0, /*!< fHOCO = 24MHz, fIH = 24MHz */
HOCO_FREQ_16MHZ = 0xE9, /*!< fHOCO = 32MHz, fIH = 16MHz */
HOCO_FREQ_12MHZ = 0xE1, /*!< fHOCO = 24MHz, fIH = 12MHz */
HOCO_FREQ_8MHZ = 0xEA, /*!< fHOCO = 32MHz, fIH = 8MHz */
HOCO_FREQ_6MHZ = 0xE2, /*!< fHOCO = 24MHz, fIH = 6MHz */
HOCO_FREQ_4MHZ = 0xEB, /*!< fHOCO = 32MHz, fIH = 4MHz */
HOCO_FREQ_3MHZ = 0xE3, /*!< fHOCO = 24MHz, fIH = 3MHz */
HOCO_FREQ_2MHZ = 0xEC, /*!< fHOCO = 32MHz, fIH = 2MHz */
HOCO_FREQ_1MHZ = 0xED /*!< fHOCO = 32MHz, fIH = 1MHz */
} hoco_freq_t;
/*----------------------------------------------------------------------------
User Option Byte
*----------------------------------------------------------------------------*/
/* ToDo: add here your necessary defines for device initialization
following is an example for different system frequencies */
//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
const uint8_t user_opt_data[4] __attribute__((used)) __attribute__((section(".ARM.__AT_0x000000C0"))) =
{
/**
* @brief WDT Control BYTE
* Please refer to the user manual for details.
* 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
* --------|---------|---------|-------|-------|-------|-------|----------
* WDTINT | WINDOW1 | WINDOW0 | WDTON | WDCS2 | WDCS1 | WDCS0 | WDSTBYON
* --------|---------|---------|-------|-------|-------|-------|----------
*/
// <h> WDT Control Option Byte (C0H)
// <e.4> Enable WDT (WDTON)
// <o.5..6> Watchdog timer window open period setting <2=> 75% <3=> 100%
// <o.1..3> Watchdog timer overflow time setting <0=> 2^6/fIL <1=> 2^7/fIL
// <2=> 2^8/fIL <3=> 2^9/fIL
// <4=> 2^11/fIL <5=> 2^13/fIL
// <6=> 2^14/fIL <7=> 2^16/fIL
// <e.0> Operation in Standby mode setting (WDSTBYON)
// <i> WDT Operaton in SLEEP/DEEPSLEEP mode.
// </e>
// <e.7> interrupt enable
// <i> interval interrupt is generated when 75% + 1/2 fIL of the overflow time is reached.
// </e>
// </e>
// </h>
0xEF,
/**
* @brief LVD Control BYTE (C1H)
* Please refer to the user manual for details.
* 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
* -------|-------|-------|-------|-------|-------|---------|----------
* VPOC2 | VPOC1 | VPOC0 | 1 | LVIS1 | LVIS0 | LVIMDS1 | LVIMDS0
* -------|-------|-------|-------|-------|-------|---------|----------
*/
// <h> LVD Control Option Byte (C1H)
// <o.0..7> Voltage detection setting (VLVD) <0xFF=> ( LVD OFF )
// <0x39=> VLVD = 1.98V/1.94V ( interrupt mode )
// <0x35=> VLVD = 2.09V/2.04V ( interrupt mode )
// <0x5D=> VLVD = 2.50V/2.45V ( interrupt mode )
// <0x59=> VLVD = 2.61V/2.55V ( interrupt mode )
// <0x55=> VLVD = 2.71V/2.65V ( interrupt mode )
// <0x7D=> VLVD = 2.81V/2.75V ( interrupt mode )
// <0x79=> VLVD = 2.92V/2.86V ( interrupt mode )
// <0x75=> VLVD = 3.02V/2.96V ( interrupt mode )
// <0x3B=> VLVD = 1.98V/1.94V ( reset mode )
// <0x37=> VLVD = 2.09V/2.04V ( reset mode )
// <0x5F=> VLVD = 2.50V/2.45V ( reset mode )
// <0x5B=> VLVD = 2.61V/2.55V ( reset mode )
// <0x57=> VLVD = 2.71V/2.65V ( reset mode )
// <0x7F=> VLVD = 2.81V/2.75V ( reset mode )
// <0x7B=> VLVD = 2.92V/2.86V ( reset mode )
// <0x77=> VLVD = 3.02V/2.96V ( reset mode )
// <0x36=> VLVDH = 2.09V/2.04V, VLVDL = 1.84V ( interrupt & reset mode )
// <0x32=> VLVDH = 3.13V/3.06V, VLVDL = 1.84V ( interrupt & reset mode )
// <0x5A=> VLVDH = 2.61V/2.55V, VLVDL = 2.45V ( interrupt & reset mode )
// <0x56=> VLVDH = 2.71V/2.65V, VLVDL = 2.45V ( interrupt & reset mode )
// <0x52=> VLVDH = 3.75V/3.67V, VLVDL = 2.45V ( interrupt & reset mode )
// <0x7A=> VLVDH = 2.92V/2.86V, VLVDL = 2.75V ( interrupt & reset mode )
// <0x76=> VLVDH = 3.02V/2.96V, VLVDL = 2.75V ( interrupt & reset mode )
// <0x72=> VLVDH = 4.06V/3.98V, VLVDL = 2.75V ( interrupt & reset mode )
// <i> Please setting the item for interrupt & reset mode
// </h>
0x3B,
/**
* @brief HOCO Control BYTE (FRQSEL)
* Please refer to the user manual for details.
* 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
* -------|-------|-------|---------|---------|---------|---------|---------
* 1 | 1 | 1 | FRQSEL4 | FRQSEL3 | FRQSEL2 | FRQSEL1 | FRQSEL0
* -------|-------|-------|---------|---------|---------|---------|---------
*/
// <h> HOCO Control Option Byte (C2H)
// <o.0..4> High-speed OCO clock setting <0xF8=> fHOCO = 64MHz, fIH = 64MHz
// <0xF0=> fHOCO = 48MHz, fIH = 48MHz
// <0xE8=> fHOCO = 32MHz, fIH = 32MHz
// <0xE0=> fHOCO = 24MHz, fIH = 24MHz
// <0xE9=> fHOCO = 32MHz, fIH = 16MHz
// <0xE1=> fHOCO = 24MHz, fIH = 12MHz
// <0xEA=> fHOCO = 32MHz, fIH = 8MHz
// <0xE2=> fHOCO = 24MHz, fIH = 6MHz
// <0xEB=> fHOCO = 32MHz, fIH = 4MHz
// <0xE3=> fHOCO = 24MHz, fIH = 3MHz
// <0xEC=> fHOCO = 32MHz, fIH = 2MHz
// <0xED=> fHOCO = 32MHz, fIH = 1MHz
// </h>
0xE8,
/**
* @brief Flash Protect Control BYTE
* Please refer to the user manual for details.
*/
// <h> OCD Control Option Byte (C3H)
// <o.0..7> On-chip debug setting (OCDEN) <0xFF=> Enable <0xC3=> Disable
// <i> OCDM(500004H) == 0x3C && OCDEN == 0xC3: Debugger can not erease/write/read Flash.
// <i> OCDM(500004H) != 0x3C && OCDEN == 0xC3: Debugger can only chip erease Flash but cannot write/read Flash.
// </h>
0xFF
};
//-------- <<< end of configuration section >>> ------------------
/** @} */ /* End of group Configuration_of_User_Option_Byte */
/*----------------------------------------------------------------------------
System Core Clock Variable
*----------------------------------------------------------------------------*/
/* ToDo: initialize SystemCoreClock with the system core clock frequency value
achieved after system intitialization.
This means system core clock frequency after call to SystemInit() */
uint32_t SystemCoreClock; /* System Clock Frequency (Core Clock)*/
/*----------------------------------------------------------------------------
Clock functions
*----------------------------------------------------------------------------*/
__WEAK uint32_t CLK_GetfIHFreq(void)
{
uint32_t freq;
uint8_t frqsel = (*(uint8_t *)0x000000C2U);
frqsel &= 0xF8; /* Mask the lower 3 bits */
frqsel |= CGC->HOCODIV; /* Refer the value of HOCODIV */
switch(frqsel)
{
case HOCO_FREQ_64MHZ:
freq = 64000000U; /* fIH = 64MHz */
break;
case HOCO_FREQ_48MHZ:
freq = 48000000U; /* fIH = 48MHz */
break;
case HOCO_FREQ_32MHZ:
freq = 32000000U; /* fIH = 32MHz */
break;
case HOCO_FREQ_24MHZ:
freq = 24000000U; /* fIH = 24MHz */
break;
case HOCO_FREQ_16MHZ:
freq = 16000000U; /* fIH = 16MHz */
break;
case HOCO_FREQ_12MHZ:
freq = 12000000U; /* fIH = 12MHz */
break;
case HOCO_FREQ_8MHZ:
freq = 8000000U; /* fIH = 8MHz */
break;
case HOCO_FREQ_6MHZ:
freq = 6000000U; /* fIH = 6MHz */
break;
case HOCO_FREQ_4MHZ:
freq = 4000000U; /* fIH = 4MHz */
break;
case HOCO_FREQ_3MHZ:
freq = 3000000U; /* fIH = 3MHz */
break;
case HOCO_FREQ_2MHZ:
freq = 2000000U; /* fIH = 2MHz */
break;
case HOCO_FREQ_1MHZ:
freq = 1000000U; /* fIH = 1MHz */
break;
default:
freq = 1000000U; /* fIH = 1MHz */
break;
}
return(freq);
}
__WEAK uint32_t CLK_GetCoreFreq(void)
{
uint32_t freq;
uint8_t pllsel = 0;
if(CGC->CKC&0x20){ // Main Osc
freq = __XTAL; /* Get XTAL frequency */
}
else{ // fIH
freq = CLK_GetfIHFreq(); /* Get fIH frequency */
if(CGC->MCKC&0x80){ /* CGC->MCKC&0x80 = 0x80: PLL On */
if (CGC->PLLCR&0x80){ // XTAL + PLL
freq = __XTAL; /* Get XTAL frequency */
}
else{ // fIH + PLL
freq = CLK_GetfIHFreq(); /* Get fIH frequency */
}
pllsel = (CGC->PLLCR >> 2)&0x03; // PLL div in PLLCR
if(pllsel>=2){ // PLL Div=4
freq = freq/4;
}
else if(pllsel==1){ // PLL Div=2
freq = freq/2;
}
else{ // PLL Div=1
freq = freq/1;
}
if((CGC->PLLCR >> 1)&0x01){ // PLL Mul in PLLCR
freq = freq*16; // PLL Mul=16
}
else{
freq = freq*12; // PLL Mul=12
}
pllsel = (CGC->MCKC>>1)&0x03; // PLL div in MCKC
if (pllsel==0){
pllsel = pllsel + 1; // 00b: Div=1
}
else if(pllsel==3){
pllsel = (pllsel+1) * 2; // 11b: (Div+1)*2=8
}
else{
pllsel = pllsel * 2; // 01~10b: (Div*2)=2or4
}
freq = freq/pllsel;
}
//else{ /* CGC->MCKC&0x80 = 0: PLL Off */
//freq = CLK_GetfIHFreq(); /* Get fIH frequency */
//}
}
return(freq);
}
__WEAK void SystemCoreClockUpdate (void) /* Get Core Clock Frequency */
{
/* ToDo: add code to calculate the system frequency based upon the current
register settings.
This function can be used to retrieve the system core clock frequeny
after user changed register sittings. */
SystemCoreClock = CLK_GetCoreFreq();
}
void SystemInit (void)
{
/* ToDo: add code to initialize the system
do not use global variables because this function is called before
reaching pre-main. RW section maybe overwritten afterwards. */
/* RAM Parity Error Reset Disable */
SAF->RPECTL = 0x80U;
CGC->WDTCFG0 = 0x1A;
CGC->WDTCFG1 = 0x2B;
CGC->WDTCFG2 = 0x3C;
CGC->WDTCFG3 = 0x4D;
DBG->DBGSTOPCR = 0;
SystemCoreClock = CLK_GetCoreFreq();
/* NVIC Clear Pending IRQ */
NVIC->ICPR[0U] = 0xFFFFFFFF;
/* NVIC Enable IRQs */
NVIC->ISER[0U] = 0xFFFFFFFF;
/* NVIC Lower Priority */
NVIC->IP[0U] = 0xC0C0C0C0;
NVIC->IP[1U] = 0xC0C0C0C0;
NVIC->IP[2U] = 0xC0C0C0C0;
NVIC->IP[3U] = 0xC0C0C0C0;
NVIC->IP[4U] = 0xC0C0C0C0;
NVIC->IP[5U] = 0xC0C0C0C0;
NVIC->IP[6U] = 0xC0C0C0C0;
NVIC->IP[7U] = 0xC0C0C0C0;
/* restart watchdog timer */
WDT->WDTE = 0xACU;
}
Firmware/Project/Cmsemicon/BAT32A279/MDK_ARM/RTE/Device/BAT32A239KK80FA/userdefine.h deleted 100644 → 0
View file @ 6e32a063
/***********************************************************************************************************************
* Copyright (C) All rights reserved.
***********************************************************************************************************************/
/***********************************************************************************************************************
* @file userdefine.h
* @brief This file includes user definition.
* @version 1.0.0
* @date 2019/12/24
***********************************************************************************************************************/
#ifndef _USER_DEF_H
#define _USER_DEF_H
/***********************************************************************************************************************
User definitions
***********************************************************************************************************************/
#ifndef __TYPEDEF__
typedef unsigned short MD_STATUS;
/* Status list definition */
#define MD_STATUSBASE (0x00U)
#define MD_OK (MD_STATUSBASE + 0x00U) /* register setting OK */
#define MD_SPT (MD_STATUSBASE + 0x01U) /* IIC stop */
#define MD_NACK (MD_STATUSBASE + 0x02U) /* IIC no ACK */
#define MD_BUSY1 (MD_STATUSBASE + 0x03U) /* busy 1 */
#define MD_BUSY2 (MD_STATUSBASE + 0x04U) /* busy 2 */
#define MD_OVERRUN (MD_STATUSBASE + 0x05U) /* IIC OVERRUN occur */
/* Error list definition */
#define MD_ERRORBASE (0x80U)
#define MD_ERROR (MD_ERRORBASE + 0x00U) /* error */
#define MD_ARGERROR (MD_ERRORBASE + 0x01U) /* error agrument input error */
#define MD_ERROR1 (MD_ERRORBASE + 0x02U) /* error 1 */
#define MD_ERROR2 (MD_ERRORBASE + 0x03U) /* error 2 */
#define MD_ERROR3 (MD_ERRORBASE + 0x04U) /* error 3 */
#define MD_ERROR4 (MD_ERRORBASE + 0x05U) /* error 4 */
#define MD_ERROR5 (MD_ERRORBASE + 0x06U) /* error 5 */
#endif
#define TRMW *((volatile uint8_t *)(0x40021C08))
#define TRMR *((volatile uint8_t *)(0x40021C0C))
#define TRMT *((volatile uint8_t *)(0x40021C10))
/***********************************************************************************************************************
Macro definitions for Clock
***********************************************************************************************************************/
#define CPU_CLOCK_FREQ 64000000UL//64MHz clock frequency
#define PLL_CLOCK
/***********************************************************************************************************************
Macro definitions for CAN
***********************************************************************************************************************/
#define CAN0_USE
#define CAN1_USE
#define CAN_REC_MASK1 0x1fffffffU
#define CAN_REC_MASK2 0x1fffffffU
#define CAN_REC_MASK3 0x1fffffffU
#define CAN_REC_MASK4 0x1fffffffU
/***********************************************************************************************************************
Macro definitions of SCI usage:
Each channel of SCI has three functions: UART, SPI, and IIC. You can only choose one function to use.
***********************************************************************************************************************/
/* ToDo: You can only define ONE of the following THREE MACROs according to your application */
#define USE_SCI_UART0_TX /*! Using CH0 of SCI0 as UART Transmitter */
//#define USE_SCI_SPI00 /*! Using CH0 of SCI0 as SPI Transmitter or Receiver */
//#define USE_SCI_IIC00 /*! Using CH0 of SCI0 as IIC Transmitter or Receiver */
/* ToDo: You can only define ONE of the following THREE MACROs according to your application */
#define USE_SCI_UART0_RX /*! Using CH1 of SCI0 as UART Receiver */
//#define USE_SCI_SPI01 /*! Using CH1 of SCI0 as SPI Transmitter or Receiver */
//#define USE_SCI_IIC01 /*! Using CH1 of SCI0 as IIC Transmitter or Receiver */
/* ToDo: You can only define ONE of the following THREE MACROs according to your application */
#define USE_SCI_UART1_TX /*! Using CH2 of SCI0 as UART Transmitter */
//#define USE_SCI_SPI10 /*! Using CH2 of SCI0 as SPI Transmitter or Receiver */
//#define USE_SCI_IIC10 /*! Using CH2 of SCI0 as IIC Transmitter or Receiver */
/* ToDo: You can only define ONE of the following THREE MACROs according to your application */
#define USE_SCI_UART1_RX /*! Using CH3 of SCI0 as UART Receiver */
//#define USE_SCI_SPI11 /*! Using CH3 of SCI0 as SPI Transmitter or Receiver */
//#define USE_SCI_IIC11 /*! Using CH3 of SCI0 as IIC Transmitter or Receiver */
/* ToDo: You can only define ONE of the following THREE MACROs according to your application */
//#define USE_SCI_UART2_TX /*! Using CH0 of SCI1 as UART Transmitter */
//#define USE_SCI_SPI20 /*! Using CH0 of SCI1 as SPI Transmitter or Receiver */
#define USE_SCI_IIC20 /*! Using CH0 of SCI1 as IIC Transmitter or Receiver */
/* ToDo: You can only define ONE of the following THREE MACROs according to your application */
//#define USE_SCI_UART2_RX /*! Using CH1 of SCI1 as UART Receiver */
//#define USE_SCI_SPI21 /*! Using CH1 of SCI1 as SPI Transmitter or Receiver */
#define USE_SCI_IIC21 /*! Using CH1 of SCI1 as IIC Transmitter or Receiver */
/* ToDo: You can only define ONE of the following THREE MACROs according to your application */
#define USE_SCI_UART3_TX /*! Using CH0 of SCI2 as UART Transmitter */
//#define USE_SCI_SPI30 /*! Using CH0 of SCI2 as SPI Transmitter or Receiver */
//#define USE_SCI_IIC30 /*! Using CH0 of SCI2 as IIC Transmitter or Receiver */
/* ToDo: You can only define ONE of the following THREE MACROs according to your application */
#define USE_SCI_UART3_RX /*! Using CH1 of SCI2 as UART Receiver */
//#define USE_SCI_SPI31 /*! Using CH1 of SCI2 as SPI Transmitter or Receiver */
//#define USE_SCI_IIC31 /*! Using CH1 of SCI2 as IIC Transmitter or Receiver */
/***********************************************************************************************************************
DMA Control Data Set definitions
***********************************************************************************************************************/
#define SPI00_WITH_DMA
#define CTRL_DATA_SPI00 0
//#define SPI01_WITH_DMA
//#define CTRL_DATA_SPI01 2
#define SPI10_WITH_DMA
#define CTRL_DATA_SPI10 4
#define SPI11_WITH_DMA
#define CTRL_DATA_SPI11 6
//#define SPI20_WITH_DMA
//#define CTRL_DATA_SPI20 8
//#define SPI21_WITH_DMA
//#define CTRL_DATA_SPI21 10
#define ADC_WITH_DMA
#define CTRL_DATA_ADC 12
#define DAC_WITH_DMA
#define CTRL_DATA_DAC 14
#define DMA_CHANNEL_NUMBER 4
#define DMA_VECTOR_BASE_SIZE 64
#define DMA_VECTOR_SIZE (DMA_VECTOR_BASE_SIZE+16*DMA_CHANNEL_NUMBER)
/** @addtogroup Peripherals_Port_Setting_Definations
* @{
*/
/* ================================================================================================================== */
/* ================ TM40 ================ */
/* ================================================================================================================== */
/**
* @brief TM40 TI00~3 and TO00~3 Port Setting (Alternative to fixed ports)
*/
#define TI00_PORT_SETTING() do{ \
PORT->PM0 |= (1 << 0); /* P00 is used as TI00 input */ \
PORT->PMC0 &= ~(1 << 0); /* P00 is digital function */ \
}while(0)
#define TI01_PORT_SETTING() do{ \
PORT->PM1 |= (1 << 6); /* P16 is used as TI01 input */ \
}while(0)
#define TI02_PORT_SETTING() do{ \
PORT->PM1 |= (1 << 7); /* P17 is used as TI02 input */ \
}while(0)
#define TI03_PORT_SETTING() do{ \
PORT->PM3 |= (1 << 1); /* P31 is used as TI03 input */ \
}while(0)
#define TO00_PORT_SETTING() do{ \
PORT->P0 &= ~(1 << 1); /* P01 output low level */ \
PORT->PM0 &= ~(1 << 1); /* P01 is used as TO00 output */ \
PORT->PMC0 &= ~(1 << 1); /* P01 is digital function */ \
}while(0)
#define TO01_PORT_SETTING() do{ \
PORT->P1 &= ~(1 << 6); /* P16 output low level */ \
PORT->PM1 &= ~(1 << 6); /* P16 is used as TO01 output */ \
}while(0)
#define TO02_PORT_SETTING() do{ \
PORT->P1 &= ~(1 << 7); /* P17 output low level */ \
PORT->PM1 &= ~(1 << 7); /* P17 is used as TO02 output */ \
}while(0)
#define TO03_PORT_SETTING() do{ \
PORT->P3 &= ~(1 << 1); /* P31 output low level */ \
PORT->PM3 &= ~(1 << 1); /* P31 is used as TO03 output */ \
}while(0)
/* ================================================================================================================== */
/* ================ TM81 ================ */
/* ================================================================================================================== */
/**
* @brief TM81 TI10~3 and TO10~3 Port Setting (Alternative to fixed ports)
*/
#define TI10_PORT_SETTING() do{ \
PORT->PM6 |= (1 << 4); /* P64 is used as TI10 input */ \
}while(0)
#define TI11_PORT_SETTING() do{ \
PORT->PM6 |= (1 << 5); /* P65 is used as TI11 input */ \
}while(0)
#define TI12_PORT_SETTING() do{ \
PORT->PM6 |= (1 << 6); /* P66 is used as TI12 input */ \
}while(0)
#define TI13_PORT_SETTING() do{ \
PORT->PM6 |= (1 << 7); /* P67 is used as TI13 input */ \
}while(0)
#define TO10_PORT_SETTING() do{ \
PORT->P6 &= ~(1 << 4); /* P64 output low level */ \
PORT->PM6 &= ~(1 << 4); /* P64 is used as TO10 output */ \
}while(0)
#define TO11_PORT_SETTING() do{ \
PORT->P6 &= ~(1 << 5); /* P65 output low level */ \
PORT->PM6 &= ~(1 << 5); /* P65 is used as TO11 output */ \
}while(0)
#define TO12_PORT_SETTING() do{ \
PORT->P6 &= ~(1 << 6); /* P66 output low level */ \
PORT->PM6 &= ~(1 << 6); /* P66 is used as TO12 output */ \
}while(0)
#define TO13_PORT_SETTING() do{ \
PORT->P6 &= ~(1 << 7); /* P67 output low level */ \
PORT->PM6 &= ~(1 << 7); /* P67 is used as TO13 output */ \
}while(0)
#define TI14_PORT_SETTING() do{ \
PORT->PM10 |= (1 << 0); /* P100 is used as TI14 input */ \
PORT->PMC10 &= ~(1 << 0); /* P100 is digital function */ \
}while(0)
#define TI15_PORT_SETTING() do{ \
PORT->PM1 |= (1 << 0); /* P110 is used as TI15 input */ \
}while(0)
#define TI16_PORT_SETTING() do{ \
PORT->PM11 |= (1 << 1); /* P111 is used as TI16 input */ \
}while(0)
#define TI17_PORT_SETTING() do{ \
PORT->PM0 |= (1 << 5); /* P05 is used as TI17 input */ \
}while(0)
#define TO14_PORT_SETTING() do{ \
PORT->P10 &= ~(1 << 0); /* P100 output low level */ \
PORT->PM10 &= ~(1 << 0); /* P100 is used as TO14 output */ \
PORT->PMC10 &= ~(1 << 0); /* P100 is digital function */ \
}while(0)
#define TO15_PORT_SETTING() do{ \
PORT->P11 &= ~(1 << 0); /* P110 output low level */ \
PORT->PM11 &= ~(1 << 0); /* P110 is used as TO15 output */ \
}while(0)
#define TO16_PORT_SETTING() do{ \
PORT->P11 &= ~(1 << 1); /* P111 output low level */ \
PORT->PM11 &= ~(1 << 1); /* P111 is used as TO16 output */ \
}while(0)
#define TO17_PORT_SETTING() do{ \
PORT->P0 &= ~(1 << 5); /* P05 output low level */ \
PORT->PM0 &= ~(1 << 5); /* P05 is used as TO17 output */ \
}while(0)
/* ================================================================================================================== */
/* ================ TMA ================ */
/* ================================================================================================================== */
/**
* @brief TAIO Port Setting (Alternative to 4 group ports)
*/
/* ToDo: You can allocate the TAIO to P01, P31, P41, or P06 with PIOR11 and PIOR10 register */
#define TAIO_PORT_SETTING() do{ \
PORT->PIOR1 |= (0 << 0); /* allocate TAIO to P01 */ \
PORT->P0 &= ~(1 << 1); /* P01 output low level */ \
PORT->PM0 &= ~(1 << 1); /* P01 is used as TAIO output */ \
PORT->POM0 &= ~(1 << 1); /* P01 is push-pull output mode */ \
}while(0)
/* ToDo: You can allocate the TAIO to P01, P31, P41, or P06 with PIOR11 and PIOR10 register */
#define TAI_PORT_SETTING() do{ \
PORT->PIOR1 |= (0 << 0); /* allocate TAIO to P01 */ \
PORT->PM0 |= (1 << 1); /* P01 is used as TAIO input */ \
}while(0)
/* ToDo: You can allocate the TAO to P30, P50, or P00 with PIOR13 and PIOR12 register */
#define TAO_PORT_SETTING() do{ \
PORT->PIOR1 |= (0 << 2); /* allocate TAO to P30 */ \
PORT->P3 &= ~(1 << 0); /* P30 output low level */ \
PORT->PM3 &= ~(1 << 0); /* P30 is used as TAO output */ \
PORT->POM3 &= ~(1 << 0); /* P30 is push-pull output mode */ \
}while(0)
/* ================================================================================================================== */
/* ================ TMB ================ */
/* ================================================================================================================== */
/**
* @brief TMB Port Setting（Alternative to fixed port)
*/
#define TBCLK0_PORT_SETTING() do{ \
PORT->PM0 |= (1 << 0); /* P00 is used as TBCLK0 input */ \
}while(0)
#define TBCLK1_PORT_SETTING() do{ \
PORT->PM0 |= (1 << 1); /* P01 is used as TBCLK1 input */ \
}while(0)
#define TBI0_PORT_SETTING() do{ \
PORT->PM5 |= (1 << 0); /* P50 is used as TBIO0 input */ \
}while(0)
#define TBI1_PORT_SETTING() do{ \
PORT->PM5 |= (1 << 1); /* P51 is used as TBIO1 input */ \
}while(0)
#define TBO0_PORT_SETTING() do{ \
PORT->P5 &= ~(1 << 0); /* P50 output low level */ \
PORT->PM5 &= ~(1 << 0); /* P50 is used as TBIO0 output */ \
PORT->POM5 &= ~(1 << 0); /* P50 is push-pull output mode */ \
}while(0)
#define TBO1_PORT_SETTING() do{ \
PORT->P5 &= ~(1 << 1); /* P51 output low level */ \
PORT->PM5 &= ~(1 << 1); /* P51 is used as TBIO1 output */ \
PORT->POM5 &= ~(1 << 1); /* P51 is push-pull output mode */ \
}while(0)
/* ================================================================================================================== */
/* ================ TMM ================ */
/* ================================================================================================================== */
/**
* @brief TMM Port Setting（Alternative to 3 group ports)
*/
#define TMCLK_PORT_SETTING() do{ \
PORT->PM1 |= (1 << 7); /* P17 is used as TMCLK input */ \
}while(0)
#define TMIA0_PORT_SETTING() do{ \
PORT->PM1 |= (1 << 7); /* P17 is used as TMIOA0 input */ \
}while(0)
/* ToDo: You can allocate the TMIOB0 to P14, P12, or P15 with PIOR37 and PIOR36 register */
#define TMIB0_PORT_SETTING() do{ \
PORT->PM1 |= (1 << 4); /* P14 is used as TMIOB0 input */ \
}while(0)
#define TMIC0_PORT_SETTING() do{ \
PORT->PM1 |= (1 << 6); /* P16 is used as TMIOC0 input */ \
}while(0)
/* ToDo: You can allocate the TMIOD0 to P15, P15, or P14 with PIOR37 and PIOR36 register */
#define TMID0_PORT_SETTING() do{ \
PORT->PM1 |= (1 << 5); /* P15 is used as TMIOD0 input */ \
}while(0)
/* ToDo: You can allocate the TMIOA1 to P12, P11, or P13 with PIOR37 and PIOR36 register */
#define TMIA1_PORT_SETTING() do{ \
PORT->PM1 |= (1 << 2); /* P12 is used as TMIOA1 input */ \
}while(0)
/* ToDo: You can allocate the TMIOB1 to P10, P10, or P12 with PIOR37 and PIOR36 register */
#define TMIB1_PORT_SETTING() do{ \
PORT->PM1 |= (1 << 0); /* P10 is used as TMIOB1 input */ \
}while(0)
/* ToDo: You can allocate the TMIOC1 to P13, P14, or P11 with PIOR37 and PIOR36 register */
#define TMIC1_PORT_SETTING() do{ \
PORT->PM1 |= (1 << 3); /* P13 is used as TMIOC1 input */ \
}while(0)
/* ToDo: You can allocate the TMIOD1 to P11, P13, or P10 with PIOR37 and PIOR36 register */
#define TMID1_PORT_SETTING() do{ \
PORT->PM1 |= (1 << 1); /* P11 is used as TMIOD1 input */ \
}while(0)
#define TMOA0_PORT_SETTING() do{ \
PORT->P1 &= ~(1 << 7); /* P17 output low level */ \
PORT->PM1 &= ~(1 << 7); /* P17 is used as TMIOA0 output */ \
PORT->POM1 &= ~(1 << 7); /* P17 is push-pull output mode */ \
}while(0)
#define TMOB0_PORT_SETTING() do{ \
PORT->P1 &= ~(1 << 4); /* P14 output low level */ \
PORT->PM1 &= ~(1 << 4); /* P14 is used as TMIOB0/U+ output */ \
PORT->POM1 &= ~(1 << 4); /* P14 is push-pull output mode */ \
}while(0)
#define TMOC0_PORT_SETTING() do{ \
PORT->P1 &= ~(1 << 6); /* P16 output low level */ \
PORT->PM1 &= ~(1 << 6); /* P16 is used as TMIOC0 output */ \
PORT->POM1 &= ~(1 << 6); /* P16 is push-pull output mode */ \
}while(0)
#define TMOD0_PORT_SETTING() do{ \
PORT->P1 &= ~(1 << 5); /* P15 output low level */ \
PORT->PM1 &= ~(1 << 5); /* P15 is used as TMIOD0/U- output */ \
PORT->POM1 &= ~(1 << 5); /* P15 is push-pull output mode */ \
}while(0)
#define TMOA1_PORT_SETTING() do{ \
PORT->P1 &= ~(1 << 2); /* P12 output low level */ \
PORT->PM1 &= ~(1 << 2); /* P12 is used as TMIOA1/V+ output */ \
PORT->POM1 &= ~(1 << 2); /* P12 is push-pull output mode */ \
}while(0)
#define TMOB1_PORT_SETTING() do{ \
PORT->P1 &= ~(1 << 0); /* P10 output low level */ \
PORT->PM1 &= ~(1 << 0); /* P10 is used as TMIOB1/W+ output */ \
PORT->POM1 &= ~(1 << 0); /* P10 is push-pull output mode */ \
PORT->PMC1 &= ~(1 << 0); /* P10 is digital function */ \
}while(0)
#define TMOC1_PORT_SETTING() do{ \
PORT->P1 &= ~(1 << 3); /* P13 output low level */ \
PORT->PM1 &= ~(1 << 3); /* P13 is used as TMIOC1/V- output */ \
PORT->POM1 &= ~(1 << 3); /* P13 is push-pull output mode */ \
}while(0)
#define TMOD1_PORT_SETTING() do{ \
PORT->P1 &= ~(1 << 1); /* P11 output low level */ \
PORT->PM1 &= ~(1 << 1); /* P11 is used as TMIOD1/W- output */ \
PORT->POM1 &= ~(1 << 1); /* P11 is push-pull output mode */ \
PORT->PMC1 &= ~(1 << 1); /* P11 is digital function */ \
}while(0)
#define MTR_PORT_UP_SET() do{ \
PORT->P1 |= (1 << 4); /* TMIOB0/U+ output H level */ \
}while(0)
#define MTR_PORT_UP_CLR() do{ \
PORT->P1 &= ~(1 << 4); /* TMIOB0/U+ output L level */ \
}while(0)
#define MTR_PORT_VP_SET() do{ \
PORT->P1 |= (1 << 2); /* TMIOA1/V+ output H level */ \
}while(0)
#define MTR_PORT_VP_CLR() do{ \
PORT->P1 &= ~(1 << 2); /* TMIOA1/V+ output L level */ \
}while(0)
#define MTR_PORT_WP_SET() do{ \
PORT->P1 |= (1 << 0); /* TMIOB1/W+ output H level */ \
}while(0)
#define MTR_PORT_WP_CLR() do{ \
PORT->P1 &= ~(1 << 0); /* TMIOB1/W+ output L level */ \
}while(0)
#define MTR_PORT_UN_SET() do{ \
PORT->P1 |= (1 << 5); /* TMIOD0/U- output H level */ \
}while(0)
#define MTR_PORT_UN_CLR() do{ \
PORT->P1 &= ~(1 << 5); /* TMIOD0/U- output L level */ \
}while(0)
#define MTR_PORT_VN_SET() do{ \
PORT->P1 |= (1 << 3); /* TMIOC1/V- output H level */ \
}while(0)
#define MTR_PORT_VN_CLR() do{ \
PORT->P1 &= ~(1 << 3); /* TMIOC1/V- output L level */ \
}while(0)
#define MTR_PORT_WN_SET() do{ \
PORT->P1 |= (1 << 1); /* TMIOD1/W- output H level */ \
}while(0)
#define MTR_PORT_WN_CLR() do{ \
PORT->P1 &= ~(1 << 1); /* TMIOD1/W- output L level */ \
}while(0)
/* ================================================================================================================== */
/* ================ RTC1HZ ================ */
/* ================================================================================================================== */
/**
* @brief RTC1HZ Port Setting（Alternative to fixed port)
*/
#define RTC1HZ_PORT_SETTING() do{ \
PORT->P3 &= ~(1 << 0); /* P30 output low level */ \
PORT->PM3 &= ~(1 << 0); /* P30 is used as RTC1HZ output */ \
PORT->POM3 &= ~(1 << 0); /* P30 is push-pull output mode */ \
}while(0)
/* ================================================================================================================== */
/* ================ CLKBUZ ================ */
/* ================================================================================================================== */
/**
* @brief CLKBUZ Port Setting（Alternative to 2 group ports)
*/
#if 1
/* ToDo: You can allocate the CLKBUZ0 to P140 or P31 with PIOR03 register */
#define CLKBUZ0_PORT_SETTING() do{ \
PORT->PIOR0 &= ~(1 << 3); /* allocate CLKBUZ0 to P140 */ \
PORT->P14 &= ~(1 << 0); /* P140 output low level */ \
PORT->PM14 &= ~(1 << 0); /* P140 is used as CLKBUZ0 output */ \
}while(0)
#else
/* ToDo: You can allocate the CLKBUZ0 to P140 or P31 with PIOR03 register */
#define CLKBUZ0_PORT_SETTING() do{ \
PORT->PIOR0 |= (1 << 3); /* allocate CLKBUZ0 to P31 */ \
PORT->P3 &= ~(1 << 1); /* P31 output low level */ \
PORT->PM3 &= ~(1 << 1); /* P31 is used as CLKBUZ0 output */ \
}while(0)
#endif
#if 1
/* ToDo: You can allocate the CLKBUZ1 to P141 or P55 with PIOR04 register */
#define CLKBUZ1_PORT_SETTING() do{ \
PORT->PIOR0 &= ~(1 << 4); /* allocate CLKBUZ1 to P141 */ \
PORT->P14 &= ~(1 << 1); /* P141 output low level */ \
PORT->PM14 &= ~(1 << 1); /* P141 is used as CLKBUZ1 output */ \
}while(0)
#else
/* ToDo: You can allocate the CLKBUZ1 to P141 or P55 with PIOR04 register */
#define CLKBUZ1_PORT_SETTING() do{ \
PORT->PIOR0 |= (1 << 4); /* allocate CLKBUZ1 to P55 */ \
PORT->P5 &= ~(1 << 5); /* P55 output low level */ \
PORT->PM5 &= ~(1 << 5); /* P55 is used as CLKBUZ1 output */ \
}while(0)
#endif
/* ================================================================================================================== */
/* ================ ADC ================ */
/* ================================================================================================================== */
/**
* @brief ADC Port Setting (Alternate to fixed ports)
*/
/* ToDo: Please comment out the following unused ANIx setting according to your application needs. */
//#define ADC_PORT_SETTING() do{ \
// PORT->PMC2 |= (1 << 0); /* Set ANI0(P20) pin: It is necessary for ADC_VREF_AVREFP_AVREFM, used as AVREFP */ \
// PORT->PMC2 |= (1 << 1); /* Set ANI1(P21) pin: It is necessary for ADC_VREF_AVREFP_AVREFM, used as AVREFM */ \
// PORT->PMC2 |= (1 << 2); /* Set ANI2(P22) pin */ \
// PORT->PMC2 |= (1 << 3); /* Set ANI3(P23) pin */ \
// PORT->PMC2 |= (1 << 4); /* Set ANI4(P24) pin */ \
// PORT->PMC2 |= (1 << 5); /* Set ANI5(P25) pin */ \
// PORT->PMC2 |= (1 << 6); /* Set ANI6(P26) pin */ \
// PORT->PMC2 |= (1 << 7); /* Set ANI7(P27) pin */ \
// PORT->PMC1 |= (1 << 1); /* Set ANI8(P11) pin */ \
// PORT->PMC1 |= (1 << 0); /* Set ANI9(P10) pin */ \
// PORT->PMC0 |= (1 << 3); /* Set ANI10(P03) pin */ \
// PORT->PMC0 |= (1 << 2); /* Set ANI11(P02) pin */ \
// PORT->PMC14|= (1 << 7); /* Set ANI12(P147) pin */ \
// PORT->PMC0 |= (1 << 4); /* Set ANI13(P04) pin */ \
// PORT->PMC12|= (1 << 0); /* Set ANI14(P120) pin */ \
// PORT->PMC14|= (1 << 6); /* Set ANI15(P146) pin */ \
//}while(0)
#define ADC_PORT_SETTING() do{ \
PORT->PMC2 |= (1 << 0); /* Set ANI0(P20) pin: It is necessary for ADC_VREF_AVREFP_AVREFM, used as AVREFP */ \
PORT->PMC2 |= (1 << 1); /* Set ANI1(P21) pin: It is necessary for ADC_VREF_AVREFP_AVREFM, used as AVREFM */ \
PORT->PMC2 |= (1 << 2); /* Set ANI2(P22) pin */ \
PORT->PMC2 |= (1 << 3); /* Set ANI3(P23) pin */ \
}while(0)
/* ================================================================================================================== */
/* ================ DAC ================ */
/* ================================================================================================================== */
/**
* @brief DAC Port Setting (Alternate to fixed ports)
*/
#define DAC0_PORT_SETTING() do{ \
PORT->PMC2 |= (1 << 2); /* Set ANO0(P22) pin */ \
}while(0)
#define DAC1_PORT_SETTING() do{ \
PORT->PMC2 |= (1 << 3); /* Set ANO1(P23) pin */ \
}while(0)
/* ================================================================================================================== */
/* ================ CMP ================ */
/* ================================================================================================================== */
/**
* @brief CMP Port Setting (Analog input alternate to fixed ports, digital output alternate to 2 group ports)
*/
#if 1
/* ToDo: You can allocate the VCOUT0 to P120 or P71 with PIOR20 register */
#define VCOUT0_PORT_SETTING() do { \
PORT->PIOR3 |= (1 << 1); /* VCOUT0 output enable */ \
PORT->PIOR2 &= ~(1 << 0); /* allocate VCOUT0 to P120 */ \
PORT->P12 &= ~(1 << 0); /* P120 output low level */ \
PORT->PM12 &= ~(1 << 0); /* VCOUT0 output to P120 */ \
PORT->PMC12 &= ~(1 << 0); /* P120 is digital function */ \
}while(0)
#else
/* ToDo: You can allocate the VCOUT0 to P120 or P71 with PIOR20 register */
#define VCOUT0_PORT_SETTING() do { \
PORT->PIOR3 |= (1 << 1); /* VCOUT0 output enable */ \
PORT->PIOR2 |= (1 << 0); /* allocate VCOUT0 to P71 */ \
PORT->P7 &= ~(1 << 1); /* P71 output low level */ \
PORT->PM7 &= ~(1 << 1); /* VCOUT0 output to P71 */ \
}while(0)
#endif
#if 1
/* ToDo: You can allocate the VCOUT1 to P31 or P70 with PIOR21 register */
#define VCOUT1_PORT_SETTING() do { \
PORT->PIOR3 |= (1 << 2); /* VCOUT1 output enable */ \
PORT->PIOR2 &= ~(1 << 1); /* allocate VCOUT1 to P31 */ \
PORT->P3 &= ~(1 << 1); /* P31 output low level */ \
PORT->PM3 &= ~(1 << 1); /* VCOUT1 output to P31 */ \
}while(0)
#else
#define VCOUT1_PORT_SETTING() do { \
PORT->PIOR3 |= (1 << 2); /* VCOUT1 output enable */ \
PORT->PIOR2 |= (1 << 1); /* allocate VCOUT1 to P70 */ \
PORT->P7 &= ~(1 << 0); /* P70 output low level */ \
PORT->PM7 &= ~(1 << 0); /* VCOUT1 output to P70 */ \
}while(0)
#endif
/* ToDo: Please comment out the VREF0 setting if don't used VREF0 as negative(-) side input of CMP */
#define CMP0_PORT_SETTING() do{ \
PORT->PMC2 |= (1 << 2); /* Set VCIN0(P22) pin */ \
PORT->PMC14 |= (1 << 7); /* Set VREF0(P147) pin */ \
VCOUT0_PORT_SETTING(); /* ToDo: Please delete me if you don't output VCOUT0 signal to port */ \
}while(0)
/* ToDo: Please comment out the VCINxx setting if don't used it as positive(+) side input of CMP */
#define CMP1_PORT_SETTING() do{ \
PORT->PMC0 |= (1 << 2); /* Set VCIN10(P02) pin */ \
PORT->PMC0 |= (1 << 3); /* Set VCIN11(P03) pin */ \
PORT->PMC2 |= (1 << 0); /* Set VCIN12(P20) pin */ \
PORT->PMC2 |= (1 << 1); /* Set VCIN13(P21) pin */ \
VCOUT1_PORT_SETTING(); /* ToDo: Please delete me if you don't output VCOUT1 signal to port */ \
}while(0)
/* ================================================================================================================== */
/* ================ PGA ================ */
/* ================================================================================================================== */
/**
* @brief PGA Port Setting (Alternate to fixed ports)
*/
#define PGA0O_PORT_SETTING() do { \
PORT->PMC2 |= (1 << 0); /* PGA0O output to P20 */ \
}while(0)
#define PGA1O_PORT_SETTING() do { \
PORT->PMC2 |= (1 << 1); /* PGA1O output to P21 */ \
}while(0)
#define PGA0IN_PORT_SETTING() do { \
PORT->PMC2 |= (1 << 2); /* PGA0IN input from P22 */ \
}while(0)
#define PGA0GND_PORT_SETTING() do { \
PORT->PMC2 |= (1 << 3); /* PGA0GND input from P23 */ \
}while(0)
#define PGA1IN_PORT_SETTING() do { \
PORT->PMC2 |= (1 << 4); /* PGA1IN input from P24 */ \
}while(0)
#define PGA1GND_PORT_SETTING() do { \
PORT->PMC2 |= (1 << 5); /* PGA1GND input from P25 */ \
}while(0)
/* ================================================================================================================== */
/* ================ SCI0 ================ */
/* ================================================================================================================== */
/* ToDo: You can allocate the TXD0, RXD0, SCLK00, SDI00, SDO00, SCL00 and SDA00 to the following ports with PIOR register */
/* PIOR35 PIOR34 PIOR01 : TXD0 RXD0 SCLK00 SDO00 SDI00 SCL00 SDA00
* 0 0 0 : P51 P50 P30 P51 P50 P30 P50 # default setting
* 0 0 1 : P17 P16 P55 P17 P16 - -
* 0 1 X : P40 P137 - - - - -
* 1 X X : P12 P11 - - - - -
*/
/**
* @brief UART0 Port Setting（Alternative to 4 group ports)
*/
#if 1
/* ToDo: You can allocate the TXD0 to P51, P17, P40 or P12 with PIOR35, PIOR43 and PIOR01 register */
#define TXD0_PORT_SETTING() do{ \
PORT->PIOR0 &= ~(1 << 1); /* allocate TXD0 to P51 */ \
PORT->P5 |= (1 << 1); /* P51 output high level */ \
PORT->PM5 &= ~(1 << 1); /* P51 is used as TXD0 output */ \
PORT->POM5 &= ~(1 << 1); /* P51 is push-pull output mode */ \
}while(0)
/* ToDo: You can allocate the RXD0 to P50, P16, P137 or P11 with PIOR35, PIOR43 and PIOR01 register */
#define RXD0_PORT_SETTING() do{ \
PORT->PIOR0 &= ~(1 << 1); /* allocate RXD0 to P50 */ \
PORT->PM5 |= (1 << 0); /* P50 is used as RXD0 input */ \
}while(0)
#else
/* ToDo: You can allocate the TXD0 to P51, P17, P40 or P12 with PIOR35, PIOR43 and PIOR01 register */
#define TXD0_PORT_SETTING() do{ \
PORT->PIOR0 |= (1 << 1); /* allocate TXD0 to P17 */ \
PORT->P1 |= (1 << 7); /* P17 output high level */ \
PORT->PM1 &= ~(1 << 7); /* P17 is used as TXD0 output */ \
PORT->POM1 &= ~(1 << 7); /* P17 is push-pull output mode */ \
}while(0)
/* ToDo: You can allocate the RXD0 to P50, P16, P137 or P11 with PIOR35, PIOR43 and PIOR01 register */
#define RXD0_PORT_SETTING() do{ \
PORT->PIOR0 |= (1 << 1); /* allocate RXD0 to P16 */ \
PORT->PM1 |= (1 << 6); /* P16 is used as RXD0 input */ \
}while(0)
#endif
/**
* @brief SPI00 Port Setting（Alternative to 2 group ports)
*/
#define SS00_PORT_SETTING() do{ \
PORT->PM6 |= (1 << 2); /* P62 is used as SS00 input */ \
}while(0)
#define SS00_PORT_SET() do{ \
PORT->P6 |= (1 << 2); /* P62 output high level */ \
}while(0)
#define SS00_PORT_CLR() do{ \
PORT->P6 &= ~(1 << 2); /* P62 output low level */ \
}while(0)
/* ToDo: You can allocate the SCLK00 to P30 or P55 with PIOR01 register */
#define SCLKI00_PORT_SETTING() do{ \
PORT->PIOR0 &= ~(1 << 1); /* allocate SCLKI00 to P30 */ \
PORT->PM3 |= (1 << 0); /* P30 is used as SCLK00 input */ \
}while(0)
/* ToDo: You can allocate the SCLK00 to P30 or P55 with PIOR01 register */
#define SCLKO00_PORT_SETTING() do{ \
PORT->PIOR0 &= ~(1 << 1); /* allocate SCLKI00 to P30 */ \
PORT->P3 |= (1 << 0); /* P30 output high level */ \
PORT->PM3 &= ~(1 << 0); /* P30 is used as SCLK00 output */ \
PORT->POM3 &= ~(1 << 0); /* P30 is push-pull output mode */ \
}while(0)
/* ToDo: You can allocate the SDO00 to P51 or P17 with PIOR01 register */
#define SDO00_PORT_SETTING() do{ \
PORT->PIOR0 &= ~(1 << 1); /* allocate SDO00 to P51 */ \
PORT->P5 |= (1 << 1); /* P51 output high level */ \
PORT->PM5 &= ~(1 << 1); /* P51 is used as SDO00 output */ \
PORT->POM5 &= ~(1 << 1); /* P51 is push-pull output mode */ \
}while(0)
/* ToDo: You can allocate the SDI00 to P50 or P16 with PIOR01 register */
#define SDI00_PORT_SETTING() do{ \
PORT->PIOR0 &= ~(1 << 1); /* allocate SDI00 to P50 */ \
PORT->PM5 |= (1 << 0); /* P50 is used as SDI00 input */ \
}while(0)
/**
* @brief IIC00 Port Setting（Alternative to fixed port)
*/
#define SCL00_PORT_SETTING() do{ \
PORT->PIOR0 &= ~(1 << 1); /* allocate SCL00 to P30 */ \
PORT->P3 |= (1 << 0); /* P30 output high level */ \
PORT->PM3 &= ~(1 << 0); /* P30 is used as SCL00 output */ \
PORT->POM3 |= (1 << 0); /* P30 is N-ch open-drain output mode */ \
}while(0)
#define SDA00_PORT_SETTING() do{ \
PORT->PIOR0 &= ~(1 << 1); /* allocate SDA00 to P50 */ \
PORT->P5 |= (1 << 0); /* P50 output high level */ \
PORT->PM5 &= ~(1 << 0); /* P50 is used as SDA00 inout */ \
PORT->POM5 |= (1 << 0); /* P50 is N-ch open-drain output mode */ \
}while(0)
/**
* @brief SPI01 Port Setting (Alternative to fixed port)
*/
/* ToDo: You can allocate the SS01 to any desired pins */
#define SS01_PORT_SETTING() do{ \
PORT->P6 |= (1 << 2); /* P62 output high level */ \
PORT->PM6 &= ~(1 << 2); /* P62 is used as SS01 output */ \
}while(0)
/* ToDo: You can allocate the SS01 to any desired pins */
#define SS01_PORT_SET() do{ \
PORT->P6 |= (1 << 2); /* P62 output high level */ \
}while(0)
/* ToDo: You can allocate the SS01 to any desired pins */
#define SS01_PORT_CLR() do{ \
PORT->P6 &= ~(1 << 2); /* P62 output low level */ \
}while(0)
#define SCLKI01_PORT_SETTING() do{ \
PORT->PM7 |= (1 << 5); /* P75 is used as SCLK00 input */ \
}while(0)
#define SCLKO01_PORT_SETTING() do{ \
PORT->P7 |= (1 << 5); /* P75 output high level */ \
PORT->PM7 &= ~(1 << 5); /* P75 is used as SCLK00 output */ \
}while(0)
#define SDO01_PORT_SETTING() do{ \
PORT->P7 |= (1 << 3); /* P73 output high level */ \
PORT->PM7 &= ~(1 << 3); /* P73 is used as SDO01 output */ \
}while(0)
#define SDI01_PORT_SETTING() do{ \
PORT->PM7 |= (1 << 4); /* P74 is used as SDI01 input */ \
}while(0)
/**
* @brief IIC01 Port Setting (Alternative to fixed port)
*/
#define SCL01_PORT_SETTING() do{ \
PORT->P7 |= (1 << 5); /* P75 output high level */ \
PORT->PM7 &= ~(1 << 5); /* P75 is used as SCL01 output */ \
}while(0)
#define SDA01_PORT_SETTING() do{ \
PORT->P7 |= (1 << 4); /* P74 output high level */ \
PORT->PM7 &= ~(1 << 4); /* P74 is used as SDA01 inout */ \
PORT->POM7 |= (1 << 4); /* P74 is N-ch open-drain output mode */ \
}while(0)
/**
* @brief UART1 Port Setting (Alternative to fixed port)
*/
//#define TXD1_PORT_SETTING() do{ \
// PORT->P0 |= (1 << 2); /* P02 output high level */ \
// PORT->PM0 &= ~(1 << 2); /* P02 is used as TXD1 output */ \
// PORT->POM0 &= ~(1 << 2); /* P02 is push-pull output mode */ \
// PORT->PMC0 &= ~(1 << 2); /* P02 digital function */ \
//}while(0)
//#define RXD1_PORT_SETTING() do{ \
// PORT->PM0 |= (1 << 1); /* P01 is used as RXD1 input */ \
// PORT->PMC0 &= ~(1 << 1); /* P01 digital function */ \
//}while(0)
#define TXD1_PORT_SETTING() do{ \
PORT->P0 |= (1 << 2); /* P02 output high level */ \
PORT->PM0 &= ~(1 << 2); /* P02 is used as TXD1 output */ \
PORT->POM0 &= ~(1 << 2); /* P02 is push-pull output mode */ \
PORT->PMC0 &= ~(1 << 2); /* P02 digital function */ \
}while(0)
#define RXD1_PORT_SETTING() do{ \
PORT->PM0 |= (1 << 3); /* P03 is used as RXD1 input */ \
PORT->PMC0 &= ~(1 << 3); /* P03 digital function */ \
}while(0)
/**
* @brief SPI10 Port Setting (Alternative to fixed port)
*/
/* ToDo: You can allocate the SS10 to any desired pins */
#define SS10_PORT_SETTING() do{ \
PORT->P6 |= (1 << 2); /* P62 output high level */ \
PORT->PM6 &= ~(1 << 2); /* P62 is used as SS10 output */ \
}while(0)
/* ToDo: You can allocate the SS10 to any desired pins */
#define SS10_PORT_SET() do{ \
PORT->P6 |= (1 << 2); /* P62 output high level */ \
}while(0)
/* ToDo: You can allocate the SS10 to any desired pins */
#define SS10_PORT_CLR() do{ \
PORT->P6 &= ~(1 << 2); /* P62 output low level */ \
}while(0)
#define SCLKI10_PORT_SETTING() do{ \
PORT->PM0 |= (1 << 4); /* P04 is used as SCLK10 input */ \
PORT->PMC0 &= ~(1 << 4); /* P04 is digital function */ \
}while(0)
#define SCLKO10_PORT_SETTING() do{ \
PORT->P0 |= (1 << 4); /* P04 output high level */ \
PORT->PM0 &= ~(1 << 4); /* P04 is used as SCLK10 output */ \
PORT->POM0 &= ~(1 << 4); /* P04 is push-pull output mode */ \
PORT->PMC0 &= ~(1 << 4); /* P04 is digital function */ \
}while(0)
#define SDO10_PORT_SETTING() do{ \
PORT->P0 |= (1 << 2); /* P02 output high level */ \
PORT->PM0 &= ~(1 << 2); /* P02 is used as SDO10 output */ \
PORT->POM0 &= ~(1 << 2); /* P02 is push-pull output mode */ \
PORT->PMC0 &= ~(1 << 2); /* P02 is digital function */ \
}while(0)
#define SDI10_PORT_SETTING() do{ \
PORT->PM0 |= (1 << 3); /* P03 is used as SDI10 input */ \
PORT->PMC0 &= ~(1 << 3); /* P03 is digital function */ \
}while(0)
/**
* @brief IIC10 Port Setting (Alternative to fixed port)
*/
#define SCL10_PORT_SETTING() do{ \
PORT->P0 |= (1 << 4); /* P04 output */ \
PORT->PM0 &= ~(1 << 4); /* P04 is used as SCL10 output */ \
PORT->POM0 |= (1 << 4); /* P04 is N-ch open-drain output mode */ \
PORT->PMC0 &= ~(1 << 4); /* P04 is digital function */ \
}while(0)
#define SDA10_PORT_SETTING() do{ \
PORT->P0 |= (1 << 3); /* P03 output high level */ \
PORT->PM0 &= ~(1 << 3); /* P03 is used as SDA10 inout */ \
PORT->POM0 |= (1 << 3); /* P03 is N-ch open-drain output mode */ \
PORT->PMC0 &= ~(1 << 3); /* P03 is digital function */ \
}while(0)
/**
* @brief SPI11 Port Setting (Alternative to fixed port)
*/
/* ToDo: You can allocate the SS11 to any desired pins */
#define SS11_PORT_SETTING() do{ \
PORT->P6 |= (1 << 2); /* P62 output high level */ \
PORT->PM6 &= ~(1 << 2); /* P62 is used as SS11 output */ \
}while(0)
/* ToDo: You can allocate the SS11 to any desired pins */
#define SS11_PORT_SET() do{ \
PORT->P6 |= (1 << 2); /* P62 output high level */ \
}while(0)
/* ToDo: You can allocate the SS11 to any desired pins */
#define SS11_PORT_CLR() do{ \
PORT->P6 &= ~(1 << 2); /* P62 output low level */ \
}while(0)
#define SCLKI11_PORT_SETTING() do{ \
PORT->PM1 |= (1 << 0); /* P10 is used as SCLK11 input */ \
PORT->PMC1 &= ~(1 << 0); /* P10 is digital function */ \
}while(0)
#define SCLKO11_PORT_SETTING() do{ \
PORT->P1 |= (1 << 0); /* P10 output high level */ \
PORT->PM1 &= ~(1 << 0); /* P10 is used as SCLK11 output */ \
PORT->POM1 &= ~(1 << 0); /* P10 is push-pull output mode */ \
PORT->PMC1 &= ~(1 << 0); /* P10 is digital function */ \
}while(0)
#define SDO11_PORT_SETTING() do{ \
PORT->P1 |= (1 << 2); /* P12 output high level */ \
PORT->PM1 &= ~(1 << 2); /* P12 is used as SDO11 output */ \
PORT->POM1 &= ~(1 << 2); /* P12 is push-pull output mode */ \
PORT->PMC1 &= ~(1 << 2); /* P12 is digital function */ \
}while(0)
#define SDI11_PORT_SETTING() do{ \
PORT->PM1 |= (1 << 1); /* P11 is used as SDI11 input */ \
PORT->PMC1 &= ~(1 << 1); /* P11 is digital function */ \
}while(0)
/**
* @brief IIC11 Port Setting (Alternative to fixed port)
*/
#define SCL11_PORT_SETTING() do{ \
PORT->P1 |= (1 << 0); /* P10 output high level */ \
PORT->PM1 &= ~(1 << 0); /* P10 is used as SCL11 output */ \
PORT->POM1 |= (1 << 0); /* P10 is N-ch open-drain output mode */ \
PORT->PMC1 &= ~(1 << 0); /* P10 digital function */ \
}while(0)
#define SDA11_PORT_SETTING() do{ \
PORT->P1 |= (1 << 1); /* P11 output high level */ \
PORT->PM1 &= ~(1 << 1); /* P11 is used as SDA11 inout */ \
PORT->POM1 |= (1 << 1); /* P11 is N-ch open-drain output mode */ \
PORT->PMC1 &= ~(1 << 1); /* P11 is digital function */ \
}while(0)
/* ================================================================================================================== */
/* ================ SCI1 ================ */
/* ================================================================================================================== */
/* PIOR01 : TXD2 RXD2
* 0 P13 P14
* 1 P77 P76
*/
/**
* @brief UART2 Port Setting（Alternative to 2 group ports for 64pin product)
*/
#if 1
/* ToDo: You can allocate the TXD2 to P13 or P77 with PIOR01 register */
#define TXD2_PORT_SETTING() do{ \
PORT->PIOR0 &= ~(1 << 1); /* allocate TXD2 to P13 */ \
PORT->P1 |= (1 << 3); /* P13 output high level */ \
PORT->PM1 &= ~(1 << 3); /* P13 is used as TXD2 output */ \
PORT->POM1 &= ~(1 << 3); /* P13 is push-pull output mode */ \
PORT->PMC1 &= ~(1 << 3); /* P13 is digital function */ \
}while(0)
/* ToDo: You can allocate the RXD2 to P14 or P76 with PIOR01 register */
#define RXD2_PORT_SETTING() do{ \
PORT->PIOR0 &= ~(1 << 1); /* allocate RXD2 to P14 */ \
PORT->PM1 |= (1 << 4); /* P14 is used as RXD2 input */ \
PORT->PMC1 &= ~(1 << 4); /* P14 is digital function */ \
}while(0)
#else
/* ToDo: You can allocate the TXD2 to P13 or P77 with PIOR01 register */
#define TXD2_PORT_SETTING() do{ \
PORT->PIOR0 |= (1 << 1); /* allocate TXD2 to P77 */ \
PORT->P7 |= (1 << 7); /* P77 output high level */ \
PORT->PM7 &= ~(1 << 7); /* P77 is used as TXD2 output */ \
PORT->POM7 &= ~(1 << 7); /* P77 is push-pull output mode */ \
}while(0)
/* ToDo: You can allocate the RXD2 to P14 or P76 with PIOR01 register */
#define RXD2_PORT_SETTING() do{ \
PORT->PIOR0 |= (1 << 1); /* allocate RXD2 to P76 */ \
PORT->PM7 |= (1 << 4); /* P76 is used as RXD2 input */ \
}while(0)
#endif
/**
* @brief SPI20 Port Setting（Alternative to fixed port)
*/
/* ToDo: You can allocate the SS20 to any desired pins */
#define SS20_PORT_SETTING() do{ \
PORT->P6 |= (1 << 3); /* P63 output high level */ \
PORT->PM6 &= ~(1 << 3); /* P63 is used as SS20 output */ \
}while(0)
/* ToDo: You can allocate the SS20 to any desired pins */
#define SS20_PORT_SET() do{ \
PORT->P6 |= (1 << 3); /* P63 output high level */ \
}while(0)
/* ToDo: You can allocate the SS20 to any desired pins */
#define SS20_PORT_CLR() do{ \
PORT->P6 &= ~(1 << 3); /* P63 output low level */ \
}while(0)
#define SCLKI20_PORT_SETTING() do{ \
PORT->PIOR0 &= ~(1 << 1); /* allocate SCLK20 to P15 */ \
PORT->PM1 |= (1 << 5); /* P15 is used as SCLK20 input */ \
}while(0)
#define SCLKO20_PORT_SETTING() do{ \
PORT->PIOR0 &= ~(1 << 1); /* allocate SCLK20 to P15 */ \
PORT->P1 |= (1 << 5); /* P15 output high level */ \
PORT->PM1 &= ~(1 << 5); /* P15 is used as SCLK20 output */ \
PORT->POM1 &= ~(1 << 5); /* P15 is push-pull output mode */ \
}while(0)
#define SDO20_PORT_SETTING() do{ \
PORT->PIOR0 &= ~(1 << 1); /* allocate SDO20 to P15 */ \
PORT->P1 |= (1 << 3); /* P13 output high level */ \
PORT->PM1 &= ~(1 << 3); /* P13 is used as SDO20 output */ \
PORT->POM1 &= ~(1 << 3); /* P13 is push-pull output mode */ \
}while(0)
#define SDI20_PORT_SETTING() do{ \
PORT->PIOR0 &= ~(1 << 1); /* allocate SDI20 to P14 */ \
PORT->PM1 |= (1 << 4); /* P14 is used as SDI20 input */ \
}while(0)
/**
* @brief IIC20 Port Setting（Alternative to fixed port)
*/
#define SCL20_PORT_SETTING() do{ \
PORT->PIOR0 &= ~(1 << 1); /* allocate SCL20 to P15 */ \
PORT->P1 |= (1 << 5); /* P15 output high level */ \
PORT->PM1 &= ~(1 << 5); /* P15 is used as SCL20 output */ \
PORT->POM1 |= (1 << 5); /* P15 is N-ch open-drain output mode */ \
}while(0)
#define SDA20_PORT_SETTING() do{ \
PORT->PIOR0 &= ~(1 << 1); /* allocate SDA20 to P14 */ \
PORT->P1 |= (1 << 4); /* P14 output high level */ \
PORT->PM1 &= ~(1 << 4); /* P14 is used as SDA20 inout */ \
PORT->POM1 |= (1 << 4); /* P14 is N-ch open-drain output mode */ \
}while(0)
/**
* @brief SPI21 Port Setting (Alternative to fixed port)
*/
/* ToDo: You can allocate the SS21 to any desired pins */
#define SS21_PORT_SETTING() do{ \
PORT->P6 |= (1 << 3); /* P63 output high level */ \
PORT->PM6 &= ~(1 << 3); /* P63 is used as SS21 output */ \
}while(0)
/* ToDo: You can allocate the SS21 to any desired pins */
#define SS21_PORT_SET() do{ \
PORT->P6 |= (1 << 3); /* P63 output high level */ \
}while(0)
/* ToDo: You can allocate the SS21 to any desired pins */
#define SS21_PORT_CLR() do{ \
PORT->P6 &= ~(1 << 3); /* P63 output low level */ \
}while(0)
#define SCLKI21_PORT_SETTING() do{ \
PORT->PM7 |= (1 << 0); /* P70 is used as SCLK21 input */ \
}while(0)
#define SCLKO21_PORT_SETTING() do{ \
PORT->P7 |= (1 << 0); /* P70 output high level */ \
PORT->PM7 &= ~(1 << 0); /* P70 is used as SCLK21 output */ \
}while(0)
#define SDO21_PORT_SETTING() do{ \
PORT->P7 |= (1 << 2); /* P72 output high level */ \
PORT->PM7 &= ~(1 << 2); /* P72 is used as SDO21 output */ \
}while(0)
#define SDI21_PORT_SETTING() do{ \
PORT->PM7 |= (1 << 1); /* P71 is used as SDI21 input */ \
}while(0)
/**
* @brief IIC21 Port Setting (Alternative to fixed port)
*/
#define SCL21_PORT_SETTING() do{ \
PORT->P7 |= (1 << 0); /* P70 output high level */ \
PORT->PM7 &= ~(1 << 0); /* P70 is used as SCL21 output */ \
}while(0)
#define SDA21_PORT_SETTING() do{ \
PORT->P7 |= (1 << 1); /* P71 output high level */ \
PORT->PM7 &= ~(1 << 1); /* P71 is used as SDA21 inout */ \
PORT->POM7 |= (1 << 1); /* P71 is N-ch open-drain output mode */ \
}while(0)
/* ================================================================================================================== */
/* ================ SCI2 ================ */
/* ================================================================================================================== */
/*
*/
/**
* @brief UART3 Port Setting（Alternative to fixed port)
*/
#define TXD3_PORT_SETTING() do{ \
PORT->P14 |= (1 << 4); /* P144 output high level */ \
PORT->PM14 &= ~(1 << 4); /* P144 is used as TXD3 output */ \
PORT->POM14 &= ~(1 << 4); /* P144 is push-pull output mode */ \
PORT->PMC14 &= ~(1 << 4); /* P144 is digital function */ \
}while(0)
#define RXD3_PORT_SETTING() do{ \
PORT->PM14 |= (1 << 3); /* P143 is used as RXD3 input */ \
PORT->PMC14 &= ~(1 << 3); /* P143 is digital function */ \
}while(0)
/**
* @brief SPI30 Port Setting（Alternative to fixed port)
*/
/* ToDo: You can allocate the SS30 to any desired pins */
#define SS30_PORT_SETTING() do{ \
PORT->P15 |= (1 << 0); /* P150 output high level */ \
PORT->PM15 &= ~(1 << 0); /* P150 is used as SS30 output */ \
}while(0)
/* ToDo: You can allocate the SS30 to any desired pins */
#define SS30_PORT_SET() do{ \
PORT->P15 |= (1 << 0); /* P150 output high level */ \
}while(0)
/* ToDo: You can allocate the SS30 to any desired pins */
#define SS30_PORT_CLR() do{ \
PORT->P15 &= ~(1 << 0); /* P150 output low level */ \
}while(0)
#define SCLKI30_PORT_SETTING() do{ \
PORT->PM14 |= (1 << 2); /* P142 is used as SCLK30 input */ \
}while(0)
#define SCLKO30_PORT_SETTING() do{ \
PORT->P14 |= (1 << 2); /* P142 output high level */ \
PORT->PM14 &= ~(1 << 2); /* P142 is used as SCLK30 output */ \
PORT->POM14 &= ~(1 << 2); /* P142 is push-pull output mode */ \
}while(0)
#define SDO30_PORT_SETTING() do{ \
PORT->P14 |= (1 << 4); /* P144 output high level */ \
PORT->PM14 &= ~(1 << 4); /* P144 is used as SDO30 output */ \
PORT->POM14 &= ~(1 << 4); /* P144 is push-pull output mode */ \
}while(0)
#define SDI30_PORT_SETTING() do{ \
PORT->PM14 |= (1 << 3); /* P143 is used as SDI30 input */ \
}while(0)
/**
* @brief IIC30 Port Setting（Alternative to fixed port)
*/
#define SCL30_PORT_SETTING() do{ \
PORT->P14 |= (1 << 2); /* P142 output high level */ \
PORT->PM14 &= ~(1 << 2); /* P142 is used as SCL20 output */ \
PORT->POM14 |= (1 << 2); /* P142 is N-ch open-drain output mode */ \
}while(0)
#define SDA30_PORT_SETTING() do{ \
PORT->P14 |= (1 << 3); /* P143 output high level */ \
PORT->PM14 &= ~(1 << 3); /* P143 is used as SDA20 inout */ \
PORT->POM14 |= (1 << 3); /* P143 is N-ch open-drain output mode */ \
}while(0)
/**
* @brief SPI31 Port Setting (Alternative to fixed port)
*/
/* ToDo: You can allocate the SS31 to any desired pins */
#define SS31_PORT_SETTING() do{ \
PORT->P4 |= (1 << 2); /* P42 output high level */ \
PORT->PM4 &= ~(1 << 2); /* P42 is used as SS31 output */ \
}while(0)
/* ToDo: You can allocate the SS31 to any desired pins */
#define SS31_PORT_SET() do{ \
PORT->P4 |= (1 << 2); /* P42 output high level */ \
}while(0)
/* ToDo: You can allocate the SS31 to any desired pins */
#define SS31_PORT_CLR() do{ \
PORT->P4 &= ~(1 << 2); /* P42 output low level */ \
}while(0)
#define SCLKI31_PORT_SETTING() do{ \
PORT->PM4 |= (1 << 3); /* P43 is used as SCLK31 input */ \
}while(0)
#define SCLKO31_PORT_SETTING() do{ \
PORT->P4 |= (1 << 3); /* P43 output high level */ \
PORT->PM4 &= ~(1 << 3); /* P43 is used as SCLK31 output */ \
}while(0)
#define SDO31_PORT_SETTING() do{ \
PORT->P4 |= (1 << 5); /* P45 output high level */ \
PORT->PM4 &= ~(1 << 5); /* P45 is used as SDO31 output */ \
}while(0)
#define SDI31_PORT_SETTING() do{ \
PORT->PM4 |= (1 << 4); /* P44 is used as SDI31 input */ \
}while(0)
/**
* @brief IIC31 Port Setting (Alternative to fixed port)
*/
#define SCL31_PORT_SETTING() do{ \
PORT->P4 |= (1 << 3); /* P43 output high level */ \
PORT->PM4 &= ~(1 << 3); /* P43 is used as SCL31 output */ \
}while(0)
#define SDA31_PORT_SETTING() do{ \
PORT->P4 |= (1 << 4); /* P44 output high level */ \
PORT->PM4 &= ~(1 << 4); /* P44 is used as SDA31 inout */ \
PORT->POM4 |= (1 << 4); /* P44 is N-ch open-drain output mode */ \
}while(0)
/* ================================================================================================================== */
/* ================ IICA0 ================ */
/* ================================================================================================================== */
/**
* @brief IICA0 Port Setting（Alternative to 2 group ports)
*/
#if 1
/* ToDo: You can allocate the SCLA0 to P60 or P14 with PIOR02 register */
#define SCLA0_PORT_SETTING() do{ \
PORT->PIOR0 &= ~(1 << 2); /* allocate SCLA0 to P60 */ \
PORT->P6 &= ~(1 << 0); /* P60 output low level */ \
PORT->PM6 &= ~(1 << 0); /* P60 is used as SCLA0 output */ \
}while(0)
/* ToDo: You can allocate the SDAA0 to P61 or P15 with PIOR02 register */
#define SDAA0_PORT_SETTING() do{ \
PORT->PIOR0 &= ~(1 << 2); /* allocate SDAA0 to P61 */ \
PORT->P6 &= ~(1 << 1); /* P61 output low level */ \
PORT->PM6 &= ~(1 << 1); /* P61 is used as SDAA0 inout */ \
}while(0)
#else
/* ToDo: You can allocate the SCLA0 to P60 or P14 with PIOR02 register */
#define SCLA0_PORT_SETTING() do{ \
PORT->PIOR0 |= (1 << 2); /* allocate SCLA0 to P14 */ \
PORT->P1 &= ~(1 << 4); /* P14 output low level */ \
PORT->PM1 &= ~(1 << 4); /* P14 is used as SCLA0 output */ \
PORT->POM1 |= (1 << 4); /* P14 is N-ch open-drain output mode */ \
}while(0)
/* ToDo: You can allocate the SDAA0 to P61 or P15 with PIOR02 register */
#define SDAA0_PORT_SETTING() do{ \
PORT->PIOR0 |= (1 << 2); /* allocate SDAA0 to P15 */ \
PORT->P1 &= ~(1 << 5); /* P15 output low level */ \
PORT->PM1 &= ~(1 << 5); /* P15 is used as SDAA0 inout */ \
PORT->POM1 |= (1 << 5); /* P15 is N-ch open-drain output mode */ \
}while(0)
#endif
/* ================================================================================================================== */
/* ================ IICA1 ================ */
/* ================================================================================================================== */
/**
* @brief IICA1 Port Setting（Alternative to fixed port)
*/
#define SCLA1_PORT_SETTING() do{ \
PORT->P6 &= ~(1 << 2); /* P62 output low level */ \
PORT->PM6 &= ~(1 << 2); /* P62 is used as SCLA1 output */ \
}while(0)
#define SDAA1_PORT_SETTING() do{ \
PORT->P6 &= ~(1 << 3); /* P63 output low level */ \
PORT->PM6 &= ~(1 << 3); /* P63 is used as SDAA1 inout */ \
}while(0)
/* ================================================================================================================== */
/* ================ CAN0 ================ */
/* ================================================================================================================== */
/**
* @brief CAN0 Port Setting（Alternative to 2 group ports)
*/
#if 1
/* ToDo: You can allocate the CTXD0 to P02 or P51 with PIOR33 register */
#define CTXD0_PORT_SETTING() do{ \
PORT->PIOR3 &= ~(1 << 3); /* allocate CTXD0 to P02 */ \
PORT->P0 |= (1 << 2); /* P02 output high level */ \
PORT->PM0 &= ~(1 << 2); /* P02 is used as CTXD0 output */ \
PORT->PMC0 &= ~(1 << 2); /* P02 is digital function */ \
}while(0)
/* ToDo: You can allocate the CRXD0 to P03 or P50 with PIOR33 register */
#define CRXD0_PORT_SETTING() do{ \
PORT->PIOR3 &= ~(1 << 3); /* allocate CRXD0 to P03 */ \
PORT->PM0 |= (1 << 3); /* P03 is used as CRXD0 input */ \
PORT->PMC0 &= ~(1 << 3); /* P03 is digital function */ \
}while(0)
#else
/* ToDo: You can allocate the CTXD0 to P02 or P51 with PIOR33 register */
#define CTXD0_PORT_SETTING() do{ \
PORT->PIOR3 |= (1 << 3); /* allocate CTXD0 to P51 */ \
PORT->P5 |= (1 << 1); /* P51 output high level */ \
PORT->PM5 &= ~(1 << 1); /* P51 is used as CTXD0 output */ \
}while(0)
/* ToDo: You can allocate the CRXD0 to P03 or P50 with PIOR33 register */
#define CRXD0_PORT_SETTING() do{ \
PORT->PIOR3 |= (1 << 3); /* allocate CRXD0 to P50 */ \
PORT->PM5 |= (1 << 0); /* P50 is used as CRXD0 input */ \
}while(0)
#endif
/* ================================================================================================================== */
/* ================ CAN1 ================ */
/* ================================================================================================================== */
/**
* @brief CAN1 Port Setting（Alternative to fixed port)
*/
#define CTXD1_PORT_SETTING() do{ \
PORT->P6 |= (1 << 4); /* P64 output high level */ \
PORT->PM6 &= ~(1 << 4); /* P64 is used as CTXD1 output */ \
}while(0)
#define CRXD1_PORT_SETTING() do{ \
PORT->PM6 |= (1 << 5); /* P65 is used as CRXD1 input */ \
}while(0)
/* ================================================================================================================== */
/* ================ INTP ================ */
/* ================================================================================================================== */
/**
* @brief INTP Port Setting
*/
#define INTP0_PORT_SETTING() do{ \
PORT->PM13 |= (1 << 6); /* P136 is used as INTP0 input */ \
}while(0)
/* ToDo: You can allocate the INTP1 to P50 or P52 with PIOR00 register */
#define INTP1_PORT_SETTING() do{ \
PORT->PIOR0 &= ~(1 << 0); /* allocate INTP1 to P50 */ \
PORT->PM5 |= (1 << 0); /* P50 is used as INTP1 input */ \
}while(0)
/* ToDo: You can allocate the INTP2 to P51 or P53 with PIOR00 register */
#define INTP2_PORT_SETTING() do{ \
PORT->PIOR0 &= ~(1 << 0); /* allocate INTP2 to P51 */ \
PORT->PM5 |= (1 << 1); /* P51 is used as INTP2 input */ \
}while(0)
/* ToDo: You can allocate the INTP3 to P30 or P54 with PIOR00 register */
#define INTP3_PORT_SETTING() do{ \
PORT->PIOR0 &= ~(1 << 0); /* allocate INTP3 to P30 */ \
PORT->PM3 |= (1 << 0); /* P30 is used as INTP3 input */ \
}while(0)
/* ToDo: You can allocate the INTP4 to P31 or P55 with PIOR00 register */
#define INTP4_PORT_SETTING() do{ \
PORT->PIOR0 &= ~(1 << 0); /* allocate INTP4 to P31 */ \
PORT->PM3 |= (1 << 1); /* P31 is used as INTP4 input */ \
}while(0)
/* ToDo: You can allocate the INTP5 to P16 or P12 with PIOR04 register */
#define INTP5_PORT_SETTING() do{ \
PORT->PIOR0 &= ~(1 << 4); /* allocate INTP5 to P16 */ \
PORT->PM1 |= (1 << 6); /* P16 is used as INTP5 input */ \
}while(0)
#define INTP6_PORT_SETTING() do{ \
PORT->PM14 |= (1 << 0); /* P140 is used as INTP6 input */ \
}while(0)
#define INTP7_PORT_SETTING() do{ \
PORT->PM14 |= (1 << 1); /* P141 is used as INTP7 input */ \
}while(0)
/* ToDo: You can allocate the INTP8 to P74 or P42 with PIOR00 register */
#define INTP8_PORT_SETTING() do{ \
PORT->PIOR0 &= ~(1 << 0); /* allocate INTP8 to P74 */ \
PORT->PM7 |= (1 << 4); /* P74 is used as INTP8 input */ \
}while(0)
/* ToDo: You can allocate the INTP9 to P75 or P43 with PIOR00 register */
#define INTP9_PORT_SETTING() do{ \
PORT->PIOR0 &= ~(1 << 0); /* allocate INTP9 to P75 */ \
PORT->PM7 |= (1 << 5); /* P75 is used as INTP9 input */ \
}while(0)
/* ToDo: You can allocate the INTP10 to P76 or P05 with PIOR01 register */
#define INTP10_PORT_SETTING() do{ \
PORT->PIOR0 &= ~(1 << 0); /* allocate INTP10 to P76 */ \
PORT->PM7 |= (1 << 6); /* P76 is used as INTP10 input */ \
}while(0)
/* ToDo: You can allocate the INTP11 to P77 or P06 with PIOR01 register */
#define INTP11_PORT_SETTING() do{ \
PORT->PIOR0 &= ~(1 << 0); /* allocate INTP11 to P77 */ \
PORT->PM7 |= (1 << 7); /* P77 is used as INTP11 input */ \
}while(0)
/** @} */ /* End of group Peripherals_Port_Setting_Definations */
#endif
Firmware/Project/Cmsemicon/BAT32A279/MDK_ARM/RTE/Device/BAT32A279KM64FB/system_BAT32A279.c
View file @ f2cae379
...@@ -25,7 +25,7 @@ ...@@ -25,7 +25,7 @@
#include <stdint.h> #include <stdint.h>
#include "BAT32A279.h" #include "BAT32A279.h"
#include "userdefine.h"
/*---------------------------------------------------------------------------- /*----------------------------------------------------------------------------
Define clocks Define clocks
...@@ -64,7 +64,11 @@ typedef enum { ...@@ -64,7 +64,11 @@ typedef enum {
following is an example for different system frequencies */ following is an example for different system frequencies */
//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ //-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
#if (HAS_BOOTLOADER == 1U)
const uint8_t user_opt_data[4] __attribute__((used)) __attribute__((section(".ARM.__AT_0x0000C4C0"))) =
#else
const uint8_t user_opt_data[4] __attribute__((used)) __attribute__((section(".ARM.__AT_0x000000C0"))) = const uint8_t user_opt_data[4] __attribute__((used)) __attribute__((section(".ARM.__AT_0x000000C0"))) =
#endif
{ {
/** /**
......
Firmware/Project/Cmsemicon/BAT32A279/MDK_ARM/RTE/Device/BAT32A279KM64FB/userdefine.h
View file @ f2cae379
...@@ -19,6 +19,10 @@ User definitions ...@@ -19,6 +19,10 @@ User definitions
#ifndef __TYPEDEF__ #ifndef __TYPEDEF__
typedef unsigned short MD_STATUS; typedef unsigned short MD_STATUS;
#define HAS_BOOTLOADER (1u) // 仅仿真App时设置为0
#define APP_BASE (0x0000C400ul)
/* Status list definition */ /* Status list definition */
#define MD_STATUSBASE (0x00U) #define MD_STATUSBASE (0x00U)
#define MD_OK (MD_STATUSBASE + 0x00U) /* register setting OK */ #define MD_OK (MD_STATUSBASE + 0x00U) /* register setting OK */
......
Firmware/Project/Cmsemicon/BAT32A279/MDK_ARM/RTE/_HaoJin232/RTE_Components.h deleted 100644 → 0
View file @ 6e32a063
/*
* Auto generated Run-Time-Environment Configuration File
* *** Do not modify ! ***
*
* Project: 'HaoJin'
* Target: 'HaoJin232'
*/
#ifndef RTE_COMPONENTS_H
#define RTE_COMPONENTS_H
/*
* Define the Device Header File:
*/
#define CMSIS_device_header "BAT32A279.h"
#endif /* RTE_COMPONENTS_H */
Firmware/Project/Cmsemicon/BAT32A279/MDK_ARM/RTE/_HaoJin750/RTE_Components.h deleted 100644 → 0
View file @ 6e32a063
/*
* Auto generated Run-Time-Environment Configuration File
* *** Do not modify ! ***
*
* Project: 'HaoJin750TFT'
* Target: 'HaoJin750'
*/
#ifndef RTE_COMPONENTS_H
#define RTE_COMPONENTS_H
/*
* Define the Device Header File:
*/
#define CMSIS_device_header "BAT32A279.h"
#endif /* RTE_COMPONENTS_H */
Firmware/Source/System/main.c
View file @ f2cae379
...@@ -38,9 +38,16 @@ ...@@ -38,9 +38,16 @@
#include "Sys_Scheduler.h" #include "Sys_Scheduler.h"
#include "RTE.h" #include "RTE.h"
#include "Components.h" #include "Components.h"
#include "userdefine.h"
void Sys_Startup_Pre_Init(void) void Sys_Startup_Pre_Init(void)
{ {
#if (HAS_BOOTLOADER == 1u)
__disable_irq();
SCB->VTOR = APP_BASE;
__DMB();
__enable_irq();
#endif
__disable_irq(); __disable_irq();
/* soft delay, for power to stabilize */ /* soft delay, for power to stabilize */
......
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment