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haoJin750TFT
Commit f9b0a8f2 authored by 王金亮's avatar 王金亮
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✨ feat:解决休眠唤醒后，630H不跟底板通信问题 

1、唤醒后是未配置串口，也会导致无法通信的问题
2、因为休眠的时候关闭了时钟源，所以导致唤醒后没时钟，串口无法通信，现在在休眠之前配置为HSI，休眠唤醒后配置为PLL
3、更新到厂家新的CGC库
parent 1df233b0
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Showing with 174 additions and 100 deletions
Firmware/Source/Component/Components.h
View file @ f9b0a8f2
......@@ -36,6 +36,7 @@
#include "Telltales\Telltales_user.h"
#include "Telltales\Telltales_Lib.h"
#include "Application\BlueTooth.h"
#include "cgc.h"
#endif
Firmware/Source/Component/PowerManagement/PowerManag_user.c
View file @ f9b0a8f2
......@@ -44,6 +44,7 @@ static void Power_KL30_Init(void)
loc_config.u32UARTbps = 115200U;
loc_config.pfnUARTConfirmCallBack = NULL;
loc_config.pfnUARTReadMsgCallBack = Amt630hUartRecvData;
UART_DeInit(UART2);
RTE_UART_Init(UART_CH2, &loc_config);
Common_DataInit();
Analog_Signal_Conv_Init();
......@@ -76,12 +77,14 @@ static void Power_KL30_Init(void)
static void Power_Wakeup_Init(void)
{
UART_Channel_Config_st_t loc_config;
Common_DataInit();
Gpio_Init(Gpio_WakeUp_Init);
eeprom_StoreInfo_Init();
Analog_Signal_Conv_Init();
Data_User_Mileage_WakeupInit();
Sys_WakeUp_Init();
RTE_CLOCK_Select_Start(); /* 由于休眠的时候时钟关闭，唤醒的时候打开时钟，才能进行下一步 */
Data_Vehicle_Speed_KL30_Wakeup_Init();
Data_Engine_Speed_KL30_Wakeup_Init();
LINE_IN_Init();
......@@ -89,6 +92,13 @@ static void Power_Wakeup_Init(void)
Line_In_KL15_ON_Init();
Fuel_KL30_Init();
Backlight_KL30_Wakeup_Init();
RTE_UART_Sleep_Init(UART_CH2);
loc_config.u32UARTChEn = 1U;
loc_config.u32UARTbps = 115200U;
loc_config.pfnUARTConfirmCallBack = NULL;
loc_config.pfnUARTReadMsgCallBack = Amt630hUartRecvData;
UART_DeInit(UART2);
RTE_UART_Init(UART_CH2, &loc_config); /* 配置串口，630H上电发送0x0D，但是底板没回复 */
Amt630hInit();
TimerM_PWM_counter_Output_Init(TIMERM_COUNTER1, 20000, 64000000);
TimerM_PWM_CH_Output_init(TIMERM_COUNTER1, TIMERM_CHB, ActiveLevel_High);
......@@ -124,8 +134,6 @@ static void Power_IG_ON_Init(void)
Fuel_KL15_Init();
//RTE_GPIO_Set_Level(Blacklight_PWM, 1);
FaultCode_Init();
Amt630hInit();
ResetInitedState();
}
static void Power_Sleep_Init(void)
......@@ -139,10 +147,11 @@ static void Power_Sleep_Init(void)
Gpio_Init(Gpio_Sleep_Init);
AMT630H_Sleep();
Analog_Signal_Conv_Stop();
if (RTE_GPIO_Get_Level(KL15_AD_IN) == 0)/* KL15 */
{
RTE_DEEPSLEEP_Enable();
}
RTE_UART_Sleep_Init(UART_CH2);
CGC_HSI_CFG_AS_FCLK(); /* 配置时钟生成控制器(cgc)以将内部高速振荡器（HSI）作为CPU系统时钟（FCLK）以及可能的其他硬件电路的时钟源。 */
//SystemCoreClockUpdate(); /* 更新时钟频率，暂时用不上，先注释 */
RTE_DEEPSLEEP_Enable();
// RTE_CLOCK_Select_Sleep(); /* 这边代码是开启时钟，暂时用不上，先注释 */
}
static Power_Status_em Power_Stay_ON(void)
......@@ -209,6 +218,7 @@ static Power_Status_em Power_Stay_Protect(void)
if ( SYS_OPR_STAT_RUN )
{
Amt630hInit();
//CAN_TX_SetEnable(&CAN_CH0_CanMsgTxOp, CAN_N_TX_Enable);
return u8PowerSts;
}
......
Firmware/Source/Device/Cmsemicon/BAT32A279/Library/Driver/src/cgc.c
View file @ f9b0a8f2
#include "cgc.h"
uint8_t USE_HSE_SYSTYEM_CLOCK = SYSTYEM_CLOCK_CLOSE;
uint8_t USE_HSI_SYSTYEM_CLOCK = SYSTYEM_CLOCK_CLOSE;
uint8_t USE_LSE_SYSTYEM_CLOCK = SYSTYEM_CLOCK_CLOSE;
uint8_t USE_LSI_SYSTYEM_CLOCK = SYSTYEM_CLOCK_CLOSE;
/**
* @brief Enables or disables the PER0 peripheral clock.
* @note After reset, the peripheral clock (used for registers read/write access)
......@@ -107,19 +102,18 @@ void CGC_PER2PeriphClockCmd(uint32_t CGC_PER2Periph, FunctionalState NewState)
CGC->PER2 &= ~CGC_PER2Periph;
}
}
/**
* @brief Enables or disables the PER3 peripheral clock.
* @note After reset, the peripheral clock (used for registers read/write access)
* is disabled and the application software has to enable this clock before
* using it.
* @param CGC_PER2Periph: specifies the PER2 peripheral to gates its clock.
* This parameter can be any combination of the following values:
* @arg CGC_PER3Periph_LCDB: LCDB clock
* @param NewState: new state of the specified peripheral clock.
* This parameter can be: ENABLE or DISABLE.
* @retval None
*/
* @brief Enables or disables the PER3 peripheral clock.
* @note After reset, the peripheral clock (used for registers read/write access)
* is disabled and the application software has to enable this clock before
* using it.
* @param CGC_PER2Periph: specifies the PER2 peripheral to gates its clock.
* This parameter can be any combination of the following values:
* @arg CGC_PER3Periph_LCDB: LCDB clock
* @param NewState: new state of the specified peripheral clock.
* This parameter can be: ENABLE or DISABLE.
* @retval None
*/
void CGC_PER3PeriphClockCmd(uint32_t CGC_PER3Periph, FunctionalState NewState)
{
/* Check the parameters */
......@@ -155,32 +149,29 @@ void CGC_Osc_Setting(OSC_Pin_Mode_t main,OSC_Speed_Mode_t amph, OSC_Pin_Mode_t s
uint8_t tmp;
tmp = 0x00;
if(main == OSC_PORT )
if(main == OSC_OSCILLATOR)
{
tmp |= (0 << CGC_CMC_EXCLK_Pos) | (0 << CGC_CMC_OSCSEL_Pos);
tmp |= (0 << CGC_CMC_EXCLK_Pos) | (1 << CGC_CMC_OSCSEL_Pos) | (((uint8_t)amph) << CGC_CMC_AMPH_Pos);
}
if(sub == OSC_PORT )
else if(main == OSC_PORT )
{
tmp |= (0 << CGC_CMC_EXCLKS_Pos) | (0 << CGC_CMC_OSCSELS_Pos);
tmp |= (0 << CGC_CMC_EXCLK_Pos) | (0 << CGC_CMC_OSCSEL_Pos);
}
if(main == OSC_OSCILLATOR)
else if(main == OSC_EXCLK)
{
tmp |= (0 << CGC_CMC_EXCLK_Pos) | (1 << CGC_CMC_OSCSEL_Pos) | (1 << CGC_CMC_AMPH_Pos);
tmp |= (1 << CGC_CMC_EXCLK_Pos) | (1 << CGC_CMC_OSCSEL_Pos);
}
if(sub == OSC_OSCILLATOR)
{
tmp |= (0 << CGC_CMC_EXCLKS_Pos) | (1 << CGC_CMC_OSCSELS_Pos) | (1 << CGC_CMC_AMPHS_Pos);
tmp |= (0 << CGC_CMC_EXCLKS_Pos) | (1 << CGC_CMC_OSCSELS_Pos) | (((uint8_t)amphs) << CGC_CMC_AMPHS_Pos);
}
if(main == OSC_EXCLK)
else if(sub == OSC_PORT )
{
tmp |= (1 << CGC_CMC_EXCLK_Pos) | (1 << CGC_CMC_OSCSEL_Pos);
tmp |= (0 << CGC_CMC_EXCLKS_Pos) | (0 << CGC_CMC_OSCSELS_Pos);
}
if(sub == OSC_EXCLK)
else if(sub == OSC_EXCLK)
{
tmp |= (1 << CGC_CMC_EXCLKS_Pos) | (1 << CGC_CMC_OSCSELS_Pos);
}
......@@ -188,7 +179,7 @@ void CGC_Osc_Setting(OSC_Pin_Mode_t main,OSC_Speed_Mode_t amph, OSC_Pin_Mode_t s
CGC->CMC = tmp;
/* Set fMX */
CGC->CSC &= ~(1<<7) ; //MSTOP = 0
CGC->CSC &= ~(1 << CGC_CSC_MSTOP_Pos) ; //MSTOP = 0
if(main == OSC_OSCILLATOR)
{
......@@ -203,7 +194,7 @@ void CGC_Osc_Setting(OSC_Pin_Mode_t main,OSC_Speed_Mode_t amph, OSC_Pin_Mode_t s
}
/* Set fSUB */
CGC->CSC &= ~(1<<6) ; //XTSTOP = 0
CGC->CSC &= ~(1 << CGC_CSC_XTSTOP_Pos) ; //XTSTOP = 0
if(sub == OSC_OSCILLATOR)
{
......@@ -234,25 +225,24 @@ void CGC_Osc_Setting(OSC_Pin_Mode_t main,OSC_Speed_Mode_t amph, OSC_Pin_Mode_t s
*/
void CGC_LSEConfig(OSC_Pin_Mode_t sub, OSC_Power_Mode_t amphs)
{
/* Check the parameters */
assert_param(IS_CGC_LSE_MODE(sub));
assert_param(IS_CGC_LSE_PWR_MODE(amphs));
volatile uint32_t w_count;
uint8_t tmp;
/* Check the parameters */
assert_param(IS_CGC_OSC_PIN_MODE(sub));
assert_param(IS_CGC_LSE_PWR_MODE(amphs));
tmp = 0x00;
if(sub == OSC_PORT )
{
tmp |= (0 << CGC_CMC_EXCLKS_Pos) | (0 << CGC_CMC_OSCSELS_Pos);
}
if(sub == OSC_OSCILLATOR)
{
tmp |= (0 << CGC_CMC_EXCLKS_Pos) | (1 << CGC_CMC_OSCSELS_Pos) | (amphs << CGC_CMC_AMPHS_Pos);
tmp |= (0 << CGC_CMC_EXCLKS_Pos) | (1 << CGC_CMC_OSCSELS_Pos) | (((uint8_t)amphs) << CGC_CMC_AMPHS_Pos);
}
if(sub == OSC_EXCLK)
else if(sub == OSC_PORT)
{
tmp |= (0 << CGC_CMC_EXCLKS_Pos) | (0 << CGC_CMC_OSCSELS_Pos);
}
else if(sub == OSC_EXCLK)
{
tmp |= (1 << CGC_CMC_EXCLKS_Pos) | (1 << CGC_CMC_OSCSELS_Pos);
}
......@@ -260,7 +250,7 @@ void CGC_LSEConfig(OSC_Pin_Mode_t sub, OSC_Power_Mode_t amphs)
CGC->CMC = tmp;
/* Set fSUB */
CGC->CSC &= ~(1<<6) ; //XTSTOP = 0
CGC->CSC &= ~(1 << CGC_CSC_XTSTOP_Pos) ; //XTSTOP = 0
if(sub == OSC_OSCILLATOR)
{
......@@ -275,7 +265,7 @@ void CGC_LSEConfig(OSC_Pin_Mode_t sub, OSC_Power_Mode_t amphs)
/**
* @brief Configures the External High Speed oscillator (HSE).
* @note External High Speed oscillator clock source can be choose from PORT
* @note External High Speed oscillator clock source can be choose from PORT��
* OSC_OSCILLATOR or external input clock.
* at same time, OSC_OSCILLATOR can be 1MHz < fx < 10MHz or 10MHz < fx < 20MHz
* @param pinMode
......@@ -290,27 +280,25 @@ void CGC_LSEConfig(OSC_Pin_Mode_t sub, OSC_Power_Mode_t amphs)
*/
void CGC_HSEConfig(OSC_Pin_Mode_t main, OSC_Speed_Mode_t amph)
{
uint8_t temp_stab_set;
uint8_t temp_stab_wait;
uint8_t tmp;
/* Check the parameters */
assert_param(IS_CGC_LSE_MODE(main));
assert_param(IS_CGC_OSC_PIN_MODE(main));
assert_param(IS_CGC_HSE_OSC_SPEED(amph));
volatile uint32_t w_count;
uint8_t temp_stab_set;
uint8_t temp_stab_wait;
uint8_t tmp;
tmp = 0x00;
if(main == OSC_PORT )
{
tmp |= (0 << CGC_CMC_EXCLK_Pos) | (0 << CGC_CMC_OSCSEL_Pos);
}
if(main == OSC_OSCILLATOR)
{
tmp |= (0 << CGC_CMC_EXCLK_Pos) | (1 << CGC_CMC_OSCSEL_Pos) | (amph << CGC_CMC_AMPH_Pos);
tmp |= (0 << CGC_CMC_EXCLK_Pos) | (1 << CGC_CMC_OSCSEL_Pos) | (((uint8_t)amph) << CGC_CMC_AMPH_Pos);
}
if(main == OSC_EXCLK)
else if(main == OSC_PORT )
{
tmp |= (0 << CGC_CMC_EXCLK_Pos) | (0 << CGC_CMC_OSCSEL_Pos);
}
else if(main == OSC_EXCLK)
{
tmp |= (1 << CGC_CMC_EXCLK_Pos) | (1 << CGC_CMC_OSCSEL_Pos);
}
......@@ -318,7 +306,7 @@ void CGC_HSEConfig(OSC_Pin_Mode_t main, OSC_Speed_Mode_t amph)
CGC->CMC = tmp;
/* Set fMX */
CGC->CSC &= ~(1<<7) ; //MSTOP = 0
CGC->CSC &= ~(1 << CGC_CSC_MSTOP_Pos) ; //MSTOP = 0
if(main == OSC_OSCILLATOR)
{
......@@ -333,6 +321,18 @@ void CGC_HSEConfig(OSC_Pin_Mode_t main, OSC_Speed_Mode_t amph)
}
}
/* Clock switching needs to be executed in SRAM */
#if defined (__CC_ARM)
#pragma arm section code = "RW_FUNC_PLL" // Arm Compiler 5
#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION > 6010050)
#pragma clang section text = "RW_FUNC_PLL" // Arm Compiler 6
#endif
#if defined(__ICCARM__)
__ramfunc
#endif
/**
* @brief Enables External Low Speed oscillator (LSE/Fsub) used as CPU
* system clock and Clock source of peripheral hardware circuit.
......@@ -341,10 +341,13 @@ void CGC_HSEConfig(OSC_Pin_Mode_t main, OSC_Speed_Mode_t amph)
*/
void CGC_LSE_CFG_AS_FCLK()
{
CGC->CKC = (1 << CGC_CKC_CSS_Pos) | (0 << CGC_CKC_MCM0_Pos);
CGC->CKC = (1 << CGC_CKC_CSS_Pos) | (0 << CGC_CKC_MCM0_Pos);
__NOP();
__NOP();
__NOP();
__NOP();
while ((CGC->CKC & CGC_CKC_CLS_Msk) == 0);
USE_LSE_SYSTYEM_CLOCK = SYSTYEM_CLOCK_OPEN;
while ((CGC->CKC & CGC_CKC_CLS_Msk) == 0);
}
/**
......@@ -355,9 +358,12 @@ void CGC_LSE_CFG_AS_FCLK()
*/
void CGC_HSE_CFG_AS_FCLK()
{
CGC->CKC = (0 << CGC_CKC_CSS_Pos) | (1 << CGC_CKC_MCM0_Pos );
while((CGC->CKC & CGC_CKC_MCS_Msk) == 0);
USE_HSE_SYSTYEM_CLOCK = SYSTYEM_CLOCK_OPEN;
CGC->CKC = (0 << CGC_CKC_CSS_Pos) | (1 << CGC_CKC_MCM0_Pos );
__NOP();
__NOP();
__NOP();
__NOP();
while((CGC->CKC & CGC_CKC_MCS_Msk) == 0);
}
/**
......@@ -369,12 +375,48 @@ void CGC_HSE_CFG_AS_FCLK()
*/
void CGC_HSI_CFG_AS_FCLK()
{
CGC->CKC = 0 << CGC_CKC_CSS_Pos ;
if (CGC->MCKC & CGC_MCKC_CKSTR_Msk)
{
CGC->MCKC &= ~(1 << CGC_MCKC_CKSELR_Pos);
__NOP();
__NOP();
__NOP();
__NOP();
while(CGC->MCKC & CGC_MCKC_CKSTR_Msk);
}
CGC->CKC = (0 << CGC_CKC_CSS_Pos) | (0 << CGC_CKC_MCM0_Pos );
__NOP();
__NOP();
__NOP();
__NOP();
while((CGC->CKC & (CGC_CKC_CSS_Msk | CGC_CKC_MCS_Msk)));
}
while((CGC->CKC & CGC_CKC_CSS_Msk) == 1);
USE_HSI_SYSTYEM_CLOCK = SYSTYEM_CLOCK_OPEN;
/**
* @brief Enables output frequency by PLL used as CPU
* system clock and Clock source of peripheral hardware circuit.
* @note
* @retval None
*/
void CGC_PLL_CFG_AS_FCLK(void)
{
CGC->MCKC |= (1 << CGC_MCKC_CKSELR_Pos);
__NOP();
__NOP();
__NOP();
__NOP();
while((CGC->MCKC & CGC_MCKC_CKSTR_Msk) == 0);
CGC->CKC = (0 << CGC_CKC_CSS_Pos) | (0 << CGC_CKC_MCM0_Pos );
__NOP();
__NOP();
__NOP();
__NOP();
while(CGC->CKC & CGC_CKC_CSS_Msk);
}
#if 0
/**
* @brief Enables External High Speed oscillator (HSE) used as MAIN system clock
* which can provided for clock output/buzzer or CPU/peripheral hardware circuit.
......@@ -383,7 +425,11 @@ void CGC_HSI_CFG_AS_FCLK()
*/
void CGC_HSE_CFG_AS_FMAIN()
{
CGC->CKC = 1 << CGC_CKC_MCM0_Pos;
CGC->CKC = (1 << CGC_CKC_MCM0_Pos);
__NOP();
__NOP();
__NOP();
__NOP();
while((CGC->CKC & CGC_CKC_MCS_Msk) == 0);
}
/**
......@@ -394,9 +440,20 @@ void CGC_HSE_CFG_AS_FMAIN()
*/
void CGC_HSI_CFG_AS_FMAIN()
{
CGC->CKC = 0 << CGC_CKC_MCM0_Pos;
while((CGC->CKC & CGC_CKC_MCS_Msk) == 1);
CGC->CKC = (0 << CGC_CKC_MCM0_Pos);
__NOP();
__NOP();
__NOP();
__NOP();
while(CGC->CKC & CGC_CKC_MCS_Msk);
}
#endif
#if defined (__CC_ARM)
#pragma arm section code // Arm Compiler 5
#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION > 6010050)
#pragma clang section text = "" // Arm Compiler 6
#endif
/**
* @brief Setting PLL used as system clock and Clock source of peripheral hardware circuit.
......@@ -451,7 +508,7 @@ void CGC_PLL_Setting(PLL_Src_t src, PLL_Div_t div, PLL_Mul_t mul)
CGC->PLLCR = tmp;
CGC->PLLCR |= 1<<0; /* PLLON = 1 */
CGC->PLLCR |= (1 << CGC_PLLCR_PLLON_Pos); /* PLLON = 1 */
for (i = 0U; i <= 2000; i++)
{
__NOP();
......@@ -459,19 +516,6 @@ void CGC_PLL_Setting(PLL_Src_t src, PLL_Div_t div, PLL_Mul_t mul)
}
/**
* @brief Enables output frequency by PLL used as CPU
* system clock and Clock source of peripheral hardware circuit.
* @note
* @retval None
*/
__attribute__((section("RW_FUNC_PLL"))) void CGC_PLL_CFG_AS_FCLK(void)
{
CGC->MCKC = 0x01;
while((CGC->MCKC & CGC_MCKC_CKSTR_Msk) == 0);
USE_HSE_SYSTYEM_CLOCK = SYSTYEM_CLOCK_OPEN;
}
/**
* @brief This function stops the main system clock oscilator (MOSC).
* @param None
......@@ -479,7 +523,7 @@ __attribute__((section("RW_FUNC_PLL"))) void CGC_PLL_CFG_AS_FCLK(void)
*/
void CGC_MainOsc_Stop(void)
{
CGC->CSC |= 1<<7; /* MSTOP = 1 */
CGC->CSC |= (1 << CGC_CSC_MSTOP_Pos); /* MSTOP = 1 */
}
/**
......@@ -489,7 +533,7 @@ void CGC_MainOsc_Stop(void)
*/
void CGC_MainOsc_Start(void)
{
CGC->CSC &= ~(1<<7); /* MSTOP = 0 */
CGC->CSC &= ~(1 << CGC_CSC_MSTOP_Pos); /* MSTOP = 0 */
}
/**
......@@ -499,7 +543,7 @@ void CGC_MainOsc_Start(void)
*/
void CGC_SubOsc_Stop(void)
{
CGC->CSC |= 1<<6; /* XTSTOP = 1 */
CGC->CSC |= (1 << CGC_CSC_XTSTOP_Pos); /* XTSTOP = 1 */
}
/**
......@@ -509,7 +553,7 @@ void CGC_SubOsc_Stop(void)
*/
void CLK_SubOsc_Start(void)
{
CGC->CSC &= ~(1<<6); /* XTSTOP = 0 */
CGC->CSC &= ~(1 << CGC_CSC_XTSTOP_Pos); /* XTSTOP = 0 */
}
/**
......@@ -519,7 +563,7 @@ void CLK_SubOsc_Start(void)
*/
void CGC_Hoco_Stop(void)
{
CGC->CSC |= 1<<0; /* HIOSTOP = 1 */
CGC->CSC |= (1 << CGC_CSC_HIOSTOP_Pos); /* HIOSTOP = 1 */
}
/**
......@@ -529,5 +573,5 @@ void CGC_Hoco_Stop(void)
*/
void CGC_Hoco_Start(void)
{
CGC->CSC &= ~(1<<0); /* HIOSTOP = 0 */
CGC->CSC &= ~(1 << CGC_CSC_HIOSTOP_Pos); /* HIOSTOP = 0 */
}
Firmware/Source/Device/Cmsemicon/BAT32A279/Library/Driver/src/uart.c
View file @ f9b0a8f2
......@@ -68,6 +68,7 @@ void UART_DeInit(SCIAFSelect_TypeDef UARTx)
CGC_PER0PeriphClockCmd(UARTx >> 10, DISABLE);
SCIChannel_Free(UARTx, UART_Mode_Rx | UART_Mode_Tx);
}
SCIChannel_Free(UARTx, UART_Mode_Rx | UART_Mode_Tx);
}
/**
......
Firmware/Source/Device/Cmsemicon/BAT32A279/RTE/CLOCK_Select/RTE_CLOCK_Select.h
View file @ f9b0a8f2
......@@ -5,5 +5,6 @@
extern void RTE_CLOCK_Select_Start(void);
extern void RTE_CLOCK_Select_Stop(void);
extern void RTE_CLOCK_Select_Sleep(void);
#endif
Firmware/Source/Device/Cmsemicon/BAT32A279/RTE/CLOCK_Select/RTE_CLOCK_Select_BAT32A279.c
View file @ f9b0a8f2
......@@ -15,8 +15,8 @@ void RTE_CLOCK_Select_Start(void)
#ifdef USED_FX_FCLK
CGC_Osc_Setting(OSC_OSCILLATOR,OSC_UNDER_10M,OSC_OSCILLATOR,OSC_NORMAL_POWER);
CGC_PLL_Setting(PLL_SR_fMX,PLL_DIV_2,PLL_MUL_16);
CGC_PLL_CFG_AS_FCLK();
CGC_PLL_Setting(PLL_SR_fMX,PLL_DIV_2,PLL_MUL_16);/* CGC_PLL_Setting 用于配置PLL（相位锁定环）作为系统时钟以及可能的外设硬件电路的时钟源。 */
CGC_PLL_CFG_AS_FCLK(); /* PLL的输出频率配置为CPU系统时钟以及外设硬件电路的时钟源。 */
delay_init(64000000);
SystemCoreClock = 64000000UL;
#endif
......@@ -40,3 +40,20 @@ uint32_t RTE_CLOCK_Sys_Get(void)
}
void RTE_CLOCK_Select_Sleep(void)
{
uint8_t u8tempstabset1 = 0U;
uint8_t u8tempstabwait1 = 0U;
u8tempstabset1 = _FF_CGC_OSCSTAB_STA18;
do
{
u8tempstabwait1 = CGC->OSTC;
u8tempstabwait1 &= u8tempstabset1;
}
while (u8tempstabwait1 != u8tempstabset1);
CGC_PLL_Setting(PLL_SR_fMX,PLL_DIV_2,PLL_MUL_16);
CGC_PLL_CFG_AS_FCLK();//SRAM区运行
SystemCoreClock = 64000000UL;
}
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