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TianYing_ty100
Commit f0d93af9 authored by 陈家乐's avatar 陈家乐
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🐞 fix:更换CAN底层库

parent 05f25d62
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Showing with 282 additions and 76 deletions
Firmware/Source/Application/CAN_User/Can_User.c
View file @ f0d93af9
......@@ -19,7 +19,7 @@ void Can_Init(void)
Can_Config.MASK[1] = 0x000fffffU;
Can_Config.MASK[2] = 0x1fffffffU;
Can_Config.MASK[3] = 0x1fffffffU;
Can_Config.rx_callback = Can_Rx_Cak;
Can_Config.rx_callback = Read_RingBuff;//Can_Rx_Cak;
COM_CAN_Init();
rte_can_init(&Can_Config);
......@@ -36,8 +36,15 @@ void Can_Init(void)
void Can_RX_Apply_Buff(void)
{
CAN_RecvMsg.DLC = 8;
    CAN_RecvMsg.Data = {0,0,0,0,0,0,0,0};
    CAN_RecvMsg.OverWriteConfig = 0;
CAN_RecvMsg.Data[0] = 0;
CAN_RecvMsg.Data[1] = 0;
CAN_RecvMsg.Data[2] = 0;
CAN_RecvMsg.Data[3] = 0;
CAN_RecvMsg.Data[4] = 0;
CAN_RecvMsg.Data[5] = 0;
CAN_RecvMsg.Data[6] = 0;
CAN_RecvMsg.Data[7] = 0;
CAN_RecvMsg.OverWriteConfig = 0;
CAN_RecvMsg.Id = 0x101;
CAN_RecvMsg.IDE = CAN_Id_Standard;
......@@ -226,6 +233,7 @@ void Can_Rx_Cak(CanTxRxMsg *Msg)
DoCAN_L_Data_Indication((uint16_t)(Msg->Id), Msg->DLC, Msg->Data);
}
}
#if 1
/**
* @brief CAN库初始化TX/RX
*
......@@ -249,19 +257,36 @@ void CAN_TX_Init(void)
memset(pTXBuff, 0, sizeof(pTXBuff));
CAN_CH0_CanMsgTxOp.CanMsg = (st_CAN_SendOperation *)pTXBuff;
CAN_CH0_CanMsgTxOp.st_CAN_SendAttribute = CAN_CH0_CANSendAttr;
    CAN_CH0_CanMsgTxOp.Total_Msg = CAN_CH0_ID_SEND_TOTAL;
    CAN_CH0_CanMsgTxOp.Can_Write = COM_APP_Process;
    CAN_CH0_CanMsgTxOp.u8CAN_TX_ENABLE = CAN_N_TX_Disable;
CAN_CH0_CanMsgTxOp.pCAN_SendAttribute = CAN_CH0_CANSendAttr;
CAN_CH0_CanMsgTxOp.Total_Msg = CAN_CH0_ID_SEND_TOTAL;
CAN_CH0_CanMsgTxOp.Can_Write = COM_APP_Process;
CAN_CH0_CanMsgTxOp.u8CAN_TX_ENABLE = CAN_N_TX_Disable;
Can_TX_BuffInit(&CAN_CH0_CanMsgTxOp, CAN_CH0_CANSendAttr, CAN_CH0_ID_SEND_TOTAL, COM_APP_Process);
CAN_TX_SetEnable(&CAN_CH0_CanMsgTxOp, CAN_N_TX_Disable);
}
#endif
#if 0
/**
* @brief CAN库初始化TX/RX
*
*/
void COM_CAN_Init(void)
{
memset(pRXBuff, 0, sizeof(pRXBuff));
CAN_CH0_CanMsgOp.CAN_MSG_Analysis = (st_CANMsgStruct *)pRXBuff;
CAN_CH0_CanMsgOp.pAttrubute = CAN_CH0_CAN_MSG_CONST_ARRAY;
CAN_CH0_CanMsgOp.Total_Msg = CAN_CH0_ID_TOTAL_MAX;
CAN_CH0_CanMsgOp.u8CAN_RX_ENABLE = CAN_N_RX_Enable;
Can_RX_BuffInit(&CAN_CH0_CanMsgOp, CAN_CH0_CAN_MSG_CONST_ARRAY, CAN_CH0_ID_TOTAL_MAX);
CAN_RX_SetEnable(&CAN_CH0_CanMsgOp, CAN_N_RX_Enable);
memset(pTXBuff, 0, sizeof(pTXBuff));
CAN_CH0_CanMsgTxOp.CanMsg = (st_CAN_SendOperation *)pTXBuff;
Can_TX_BuffInit(&CAN_CH0_CanMsgTxOp, CAN_CH0_CANSendAttr, CAN_CH0_ID_SEND_TOTAL, COM_APP_Process);
CAN_TX_SetEnable(&CAN_CH0_CanMsgTxOp, CAN_N_TX_Enable);
}
#endif
......@@ -290,10 +315,14 @@ void Can_QuickTimer_Init(void)
* @brief Buff恢复函数
* @param deltaTime 调用时间 单位ms 10MS调用
*/
uint16_t cjl_cantest = 0;
uint16_t cjl_canflag = 0;
void Can_BusOff_Recover(uint8_t deltaTime)
{
if (get_can_busoff(CAN_CH_0) == 2)
{
cjl_canflag = 1;
CAN_TX_Count_Init();
if (RSCAN0Busoff.Status == RSCAN0_BUS_STABLE)
{
......@@ -349,6 +378,11 @@ void Can_BusOff_Recover(uint8_t deltaTime)
RSCAN0Busoff.Timer = 0;
RSCAN0Busoff.Cnt = 0;
}
if(cjl_canflag == 1)
{
cjl_canflag = 0;
Can_RX_Apply_Buff();
}
}
}
......
Firmware/Source/Device/Cmsemicon/BAT32A239/Library/Driver/include/can.h
View file @ f0d93af9
......@@ -34,9 +34,10 @@
* @{
*/
/** @addtogroup CAN
/** @addtogroup CAN
* @{
*/
#define LIST_BUF_MAX_NUM 23
/* Exported types ------------------------------------------------------------*/
#define MAX_CAN_MSGCACHE_CNT ((uint8_t)0x10)
......@@ -132,8 +133,21 @@ typedef struct
uint8_t Data[8]; /*!< Contains the data to be transmitted. It ranges from 0
to 0xFF. */
uint8_t OverWriteConfig; /*!< Specifies the CAN message mail cache over write config
This parameter can be a value for ENABLE or DISABLE */
} CanTxRxMsg;
/**
* @brief CAN Rx message history list
*/
typedef struct
{
uint16_t Head;
uint16_t Tail;
uint16_t length;
CanTxRxMsg data[LIST_BUF_MAX_NUM];
}CANBuffList_t;
/** @defgroup CAN_InitStatus
* @{
......@@ -280,14 +294,14 @@ typedef struct
*/
#define CAN_CacheType_Tx ((uint8_t)0x00)
#define CAN_CacheType_Rx_NoMask ((uint8_t)0x01)
#define CAN_CacheType_Rx_1Mask ((uint8_t)0x02)
#define CAN_CacheType_Rx_2Mask ((uint8_t)0x03)
#define CAN_CacheType_Rx_3Mask ((uint8_t)0x04)
#define CAN_CacheType_Rx_4Mask ((uint8_t)0x05)
#define CAN_CacheType_Rx_Mask1 ((uint8_t)0x02)
#define CAN_CacheType_Rx_Mask2 ((uint8_t)0x03)
#define CAN_CacheType_Rx_Mask3 ((uint8_t)0x04)
#define CAN_CacheType_Rx_Mask4 ((uint8_t)0x05)
#define IS_CAN_CACHETYPE(TYPE) (((TYPE) == CAN_CacheType_Tx) || ((TYPE) == CAN_CacheType_Rx_NoMask) || \
((TYPE) == CAN_CacheType_Rx_1Mask) || ((TYPE) == CAN_CacheType_Rx_2Mask) || \
((TYPE) == CAN_CacheType_Rx_3Mask) || ((TYPE) == CAN_CacheType_Rx_4Mask))
((TYPE) == CAN_CacheType_Rx_Mask1) || ((TYPE) == CAN_CacheType_Rx_Mask2) || \
((TYPE) == CAN_CacheType_Rx_Mask3) || ((TYPE) == CAN_CacheType_Rx_Mask4))
/** @defgroup CAN_identifier_type
* @{
......@@ -364,6 +378,17 @@ typedef struct
#define CAN_CCTRL_AL_MASK ((uint16_t)0x0040)
#define CAN_CCTRL_VALID_MASK ((uint16_t)0x0020)
#define CAN_CCTRL_PSMODE_IDLE ((uint16_t)0x0018U)
#define CAN_CCTRL_PSMODE_SLEEP ((uint16_t)0x0810U)//0x0800U
#define CAN_CCTRL_PSMODE_STOP ((uint16_t)0x1800U)
#define CAN_CCTRL_OPMODE_IDLE ((uint16_t)0x0007U)
#define CAN_CCTRL_OPMODE_NORMAL ((uint16_t)0x0106U)//0x0100U
#define CAN_CCTRL_OPMODE_NORMAL_ABT ((uint16_t)0x0205U)//0x0200U
#define CAN_CCTRL_OPMODE_ONLY_RX ((uint16_t)0x0304U)//0x0300U
#define CAN_CCTRL_OPMODE_SHOT ((uint16_t)0x0403U)//0x0400U
#define CAN_CCTRL_OPMODE_TEST ((uint16_t)0x0502U)//0x0500U
/******************* Bit definition for CLEC register ********************/
#define CAN_CLEC_ERRNONE_MASK ((uint8_t)0x00)
#define CAN_CLEC_ERRFILL_MASK ((uint8_t)0x01)
......@@ -382,6 +407,14 @@ typedef struct
#define CAN_GET_TECS(CINFO) ((uint8_t)(((CINFO) & CAN_CINFO_TECS_MASK) >> 2))
#define CAN_GET_RECS(CINFO) ((uint8_t)(((CINFO) & CAN_CINFO_RECS_MASK) >> 0))
/******************* Bit definition for INTS register ********************/
#define CAN_INTS_TX_READ ((uint8_t)0x0001U)
#define CAN_INTS_RX_READ ((uint8_t)0x0002U)
#define CAN_INTS_ERR_READ ((uint8_t)0x0004U)
#define CAN_INTS_PERR_READ ((uint8_t)0x0008U)
#define CAN_INTS_AL_READ ((uint8_t)0x0010U)
#define CAN_INTS_WK_READ ((uint8_t)0x0020U)
/******************* Bit definition for CERC register ********************/
#define CAN_CERC_REPS_MASK ((uint16_t)0x8000)
#define CAN_CERC_REC_MASK ((uint16_t)0x7F00)
......@@ -512,8 +545,11 @@ void CAN_MessageCache_OverWriteConfig(CANMSG_Type *CANxMSGy, FunctionalState New
uint8_t CAN_Transmit(CANMSG_Type *CANxMSGy, CanTxRxMsg* TxMessage);
/* Function used to receive CAN frame data from message cache to RxMessage, timeout unit is system clock tick */
uint8_t CAN_Receive(CAN_Type* CANx, CANMSG_Type *CANxMSGy, CanTxRxMsg* RxMessage, uint32_t Timeout);
uint8_t CAN_Receive_IT(CAN_Type* CANx, CANMSG_Type *CANxMSGy, CanTxRxMsg* RxMessage);
uint8_t CAN_Receive(CAN_Type* CANx, CanTxRxMsg* RxMessage, uint32_t Timeout);
void CAN_Receive_IT(CAN_Type* CANx, CANBuffList_t *listbuf);
uint8_t CANErr_Recover(CAN_Type* CANx);
/* CAN Bus Error management functions *****************************************/
uint8_t CAN_GetLastErrorCode(CAN_Type* CANx);
......
Firmware/Source/Device/Cmsemicon/BAT32A239/Library/Driver/src/can.c
View file @ f0d93af9
......@@ -2,8 +2,8 @@
******************************************************************************
* @file can.c
* @author MCD Application Team
* @version V1.0.0
* @date 27-January-2022
* @version V1.0.1
* @date 2-April-2024
* @brief This file provides firmware functions to manage the following
* functionalities of the Controller area network (CAN) peripheral:
* + Initialization and Configuration
......@@ -92,7 +92,7 @@
#define SMODE_TIMEOUT ((uint32_t)0x0000FFFF)
/* Time out for cache init */
#define CACHE_TIMEOUT ((uint32_t)0x000000FF)
#define CACHE_TIMEOUT ((uint32_t)0x0000FFFF)
/**
* @brief Deinitializes the CAN peripheral registers to their default reset values.
......@@ -645,6 +645,16 @@ uint8_t CAN_MessageCache_Init(CANMSG_Type *CANxMSGy, CanTxRxMsg *TxRxMessage)
CANxMSGy->CMCONF &= ~CAN_MCONF_RTR;
}
/* message cache overwrite config */
if (TxRxMessage->OverWriteConfig != DISABLE)
{
CANxMSGy->CMCONF |= CAN_MCONF_OWS;
}
else
{
CANxMSGy->CMCONF &= ~CAN_MCONF_OWS;
}
/* When frame type is tx type, set frame data and length */
if (TxRxMessage->CacheType == CAN_CacheType_Tx)
{
......@@ -679,7 +689,7 @@ uint8_t CAN_MessageCache_Init(CANMSG_Type *CANxMSGy, CanTxRxMsg *TxRxMessage)
}
/**
* @brief CAN periphal for nessage cache over write config.
* @brief CAN periphal for message cache over write config.
* @param CANxMSGy: where x can be 0 to select the CAN peripheral.
* where y can be 0 to 15 to select the cache.
* @param NewState: new state of the CAN interrupts.
......@@ -725,7 +735,7 @@ uint8_t CAN_Transmit(CANMSG_Type *CANxMSGy, CanTxRxMsg* TxMessage)
CANxMSGy->CMCTRL = CAN_MCTRL_CLR_RDY;
/* Wait the operate complete */
//while (((CANxMSGy->CMCTRL & CAN_MCTRL_RDY_MASK) != 0x00) && (timeout != 0))
while (((CANxMSGy->CMCTRL & CAN_MCTRL_RDY_MASK) != 0x00) && (timeout != 0))
{
timeout--;
}
......@@ -778,13 +788,13 @@ uint8_t CAN_Transmit(CANMSG_Type *CANxMSGy, CanTxRxMsg* TxMessage)
* @retval 0 is failed and true value is success for receive data length.
* @note This function is used by polling type.
*/
uint8_t CAN_Receive(CAN_Type* CANx, CANMSG_Type *CANxMSGy, CanTxRxMsg* RxMessage, uint32_t Timeout)
uint8_t CAN_Receive(CAN_Type* CANx, CanTxRxMsg* RxMessage, uint32_t Timeout)
{
uint32_t timeout_temp = Timeout;
uint16_t reg_crgpt = 0;
volatile uint8_t cache_num = 0;
uint8_t cache_num = 0;
uint8_t recv_flag = 0;
int i = 0;
CANMSG_Type *CANxMSGy;
/* Check the parameters */
assert_param(IS_CAN_ALL_PERIPH(CANx));
......@@ -803,6 +813,7 @@ uint8_t CAN_Receive(CAN_Type* CANx, CANMSG_Type *CANxMSGy, CanTxRxMsg* RxMessage
/* clear interrupt status flag */
CANx->CINTS = CAN_FLAG_REC;
recv_flag = 1;
break;
}
}
......@@ -824,11 +835,18 @@ uint8_t CAN_Receive(CAN_Type* CANx, CANMSG_Type *CANxMSGy, CanTxRxMsg* RxMessage
return 0;
}
/* clear DN register to enable next frame data cache */
CANxMSGy->CMCTRL = CAN_MCTRL_CLR_DN;
/* Get cache number and receive data length and valid data */
cache_num = (((reg_crgpt) & CAN_CRGPT_RGPT_MASK) >> 8) & 0x0F;
if(CANx == CAN0)
{
CANxMSGy = (CANMSG_Type*)CAN0MSG00 + cache_num;
}
else if(CANx == CAN1)
{
CANxMSGy = (CANMSG_Type*)CAN1MSG00 + cache_num;
}
/* clear DN register to enable next frame data cache */
CANxMSGy->CMCTRL = CAN_MCTRL_CLR_DN;
/* judge frame type is standard or extended */
if (CANxMSGy->CMIDH & 0x8000)
......@@ -848,8 +866,7 @@ uint8_t CAN_Receive(CAN_Type* CANx, CANMSG_Type *CANxMSGy, CanTxRxMsg* RxMessage
RxMessage->DLC = CANxMSGy->CMDLC;
/* Get receive frame valid data to memory */
for(i = 0; i < RxMessage->DLC; i++)
for(int i = 0; i < RxMessage->DLC; i++)
{
RxMessage->Data[i] = *(((uint8_t *)&(CANxMSGy->CMDB0)) + i);
}
......@@ -889,55 +906,154 @@ CANMSG_Type* CAN_Get_CANxMSGy(CAN_Type* CANx)
* @retval 0 is failed and true value is success for receive data length.
* @note This function is used by interrupt type.
*/
uint8_t CAN_Receive_IT(CAN_Type* CANx, CANMSG_Type *CANxMSGy, CanTxRxMsg* RxMessage)
void CAN_Receive_IT(CAN_Type* CANx, CANBuffList_t *listbuf)
{
uint16_t reg_crgpt = 0;
// uint8_t cache_num = 0;
int i=0;
uint8_t cache_num = 0;
CANMSG_Type *CANxMSGy;
CanTxRxMsg canMsgRec;
/* Check the parameters */
assert_param(IS_CAN_ALL_PERIPH(CANx));
assert_param(IS_CAN_ALL_MSGCACHE(CANxMSGy));
assert_param(RxMessage == NULL);
/* Read CRGPT register value to memory */
reg_crgpt = CANx->CRGPT;
/* check ROVF register set or not and to clear it */
if (reg_crgpt & CAN_CRGPT_ROVF_MASK)
{
CANx->CRGPT = CAN_CRGPT_CLR_ROVF;
}
while(!(reg_crgpt & CAN_CRGPT_RHPM_MASK))
{
/* Get cache number and receive data length and valid data */
cache_num = (((reg_crgpt) & CAN_CRGPT_RGPT_MASK) >> 8) & 0x0F;
if(CANx == CAN0)
{
CANxMSGy = (CANMSG_Type*)CAN0MSG00 + cache_num;
}
else if(CANx == CAN1)
{
CANxMSGy = (CANMSG_Type*)CAN1MSG00 + cache_num;
}
/* clear DN register to enable next frame data cache */
CANxMSGy->CMCTRL = CAN_MCTRL_CLR_DN;
/* clear DN register to enable next frame data cache */
CANxMSGy->CMCTRL = CAN_MCTRL_CLR_DN;
/* judge frame type is standard or extended */
if (CANxMSGy->CMIDH & 0x8000)
{
/* Extended frame to fetch ID0~ID28 */
canMsgRec.IDE = CAN_Id_Extended;
canMsgRec.Id = ((CANxMSGy->CMIDH & 0x1FFF) << 16) | (CANxMSGy->CMIDL);
}
else
{
/* Standard frame to fetch ID18~ID28 */
canMsgRec.IDE = CAN_Id_Standard;
canMsgRec.Id = (CANxMSGy->CMIDH & 0x1FFC) >> 2;
}
/* Get receive frame data length */
canMsgRec.DLC = CANxMSGy->CMDLC;
/* Get receive frame valid data to memory */
for(int i = 0; i < canMsgRec.DLC; i++)
{
canMsgRec.Data[i] = *(((uint8_t *)&(CANxMSGy->CMDB0)) + i);
}
/* Start user code. Do not edit comment generated here */
if(listbuf->length >= LIST_BUF_MAX_NUM)
{
listbuf->length = 0;
}
listbuf->data[listbuf->Tail] = canMsgRec;
listbuf->Tail = (listbuf->Tail+1)%LIST_BUF_MAX_NUM;
listbuf->length++;
/* End user code. Do not edit comment generated here */
reg_crgpt = CANx->CRGPT;
}
}
/***********************************************************************************************************************
* Function Name: CAN0Err_recover
* @brief CAN error interrupt service routine
* @param None
* @return None
***********************************************************************************************************************/
uint8_t CANErr_Recover(CAN_Type* CANx)
{
uint8_t i;
uint16_t can0ints;
CANMSG_Type* pMsg;
uint8_t canerr = 0;
/* Check the parameters */
assert_param(IS_CAN_ALL_PERIPH(CANx));
can0ints = CANx->CINTS&0x001C;//read error interrupt flag
CANx->CINTS = can0ints; //clear error interrupt flag
/* judge frame type is standard or extended */
if (CANxMSGy->CMIDH & 0x8000)
if((can0ints & CAN_INTS_ERR_READ) && (can0ints & CAN_INTS_PERR_READ))
{
/* Extended frame to fetch ID0~ID28 */
RxMessage->IDE = CAN_Id_Extended;
RxMessage->Id = ((CANxMSGy->CMIDH & 0x1FFF) << 16) | (CANxMSGy->CMIDL);
canerr = 1;
}
else
#if 1
if(can0ints & CAN_INTS_ERR_READ)//ERR interrrupt?
{
/* Standard frame to fetch ID18~ID28 */
RxMessage->IDE = CAN_Id_Standard;
RxMessage->Id = (CANxMSGy->CMIDH & 0x1FFC) >> 2;
if(CANx->CINFO & CAN_CINFO_BOFF_MASK)//bus off?
{
//recovery bus
//clear all TRQ
if(CANx == CAN0)
{
pMsg = (CANMSG_Type*)CAN0MSG00_BASE;
}
else
{
pMsg = (CANMSG_Type*)CAN1MSG00_BASE;
}
for(i=0;i<16;i++)//clear all msg buffer TRQ
{
while(pMsg->CMCTRL & CAN_MCTRL_RDY_MASK)
{
pMsg->CMCTRL = CAN_MCTRL_CLR_RDY;//clear RDY
}
pMsg->CMCTRL = CAN_MCTRL_CLR_TRQ;//clear TRQ
pMsg++;
}
CANx->CCTRL = CAN_CCTRL_CLR_CCERC| CAN_CCTRL_CLR_AL| CAN_CCTRL_CLR_VALID| CAN_CCTRL_PSMODE_IDLE| CAN_CCTRL_OPMODE_IDLE;//CAN initialize
//Read can registor
if(CANx->CLEC)
{
CANx->CLEC = 0x00;//clear CLEC
}
//set CCERC
CANx->CCTRL = CAN_CCTRL_SET_CCERC;//clear CCERC
CANx->CCTRL = CAN_CCTRL_OPMODE_NORMAL;//CAN resume
}
}
/* Get receive frame data length */
RxMessage->DLC = CANxMSGy->CMDLC;
if(can0ints & CAN_INTS_PERR_READ)//PERR interrrupt?
{
if(CANx->CLEC)
{
CANx->CLEC = 0x00;//clear CLEC
}
}
/* Get receive frame valid data to memory */
for(i = 0; i < RxMessage->DLC; i++)
{
RxMessage->Data[i] = *(((uint8_t *)&(CANxMSGy->CMDB0)) + i);
}
/* when DN or MUC register bit is set, the frame cache data is invalid */
if ((CANxMSGy->CMCTRL & CAN_MCTRL_DN_MASK) || (CANxMSGy->CMCTRL & CAN_MCTRL_MUC_MASK))
{
return 0;
}
return RxMessage->DLC;
return canerr;
#endif
}
Firmware/Source/Device/Cmsemicon/BAT32A239/RTE/CAN/rte_can.c
View file @ f0d93af9
......@@ -3,33 +3,51 @@
#include "isr.h"
#include "rte_can.h"
CANBuffList_t CanBufList = {0};
CANMSG_Type* CANMSG;
CanTxRxMsg CAN_RecvMsg;
can_rx_callback can_rx_handler = NULL;
uint8_t Read_RingBuff(CanTxRxMsg *data)
{
if (CanBufList.length == 0)
{
return 0;
}
*data = CanBufList.data[CanBufList.Head];
CanBufList.Head = (CanBufList.Head + 1) % LIST_BUF_MAX_NUM;
CanBufList.length--;
return 1;
}
/**
* @brief CAN就收完成回调
*
* @param msg
*/
static void can_recv_handler(void *msg)
static void can_recv_handler(void)
{
INTC_ClearPendingIRQ(CAN0REC_IRQn);
if (CAN_GetFlagStatus(CAN0, CAN_FLAG_REC) != RESET)
{
CAN_ClearFlag(CAN0, CAN_FLAG_REC);
CANMSG = CAN_Get_CANxMSGy(CAN0);
CAN_Receive_IT(CAN0, CANMSG, &CAN_RecvMsg);
CAN_Receive_IT(CAN0, &CanBufList);
//Read_RingBuff(&CAN_RecvMsg);
//CAN_Receive(CAN0,&CAN_RecvMsg,100);
if (can_rx_handler != NULL)
{
can_rx_handler(&CAN_RecvMsg);
Can_Rx_Cak(&CAN_RecvMsg);
}
}
}
static void can_error_handler(void)
{
INTC_ClearPendingIRQ(CAN0ERR_IRQn);
//CANErr_Recover(CAN0);
}
/**
* @brief CAN初始�?
*
......@@ -51,7 +69,7 @@ uint8_t rte_can_init(can_config_st_t *config)
GPIO_InitStruct.GPIO_Mode = GPIO_Mode_OUT;
GPIO_InitStruct.GPIO_Level = GPIO_Level_HIGH;
GPIO_InitStruct.GPIO_Ctrl = GPIO_Control_DIG;
GPIO_InitStruct.GPIO_OType = GPIO_OType_PP;
//GPIO_InitStruct.GPIO_OType = GPIO_OType_PP;
GPIO_Init(GPIO_PORT5, &GPIO_InitStruct);
/* CRXD pin init */
......@@ -85,11 +103,13 @@ uint8_t rte_can_init(can_config_st_t *config)
CAN_OperatingModeRequest(CAN0, CAN_OpMode_Normal);
CAN_ITConfig(CAN0, CAN_IT_REC, ENABLE);
CAN_ITConfig(CAN0, CAN_IT_REC | CAN_IT_ERR_STATE | CAN_IT_ERR_PROTO, ENABLE); // |CAN_IT_TRX
ISR_Register(CAN0REC_IRQn, can_recv_handler);
INTC_EnableIRQ(CAN0REC_IRQn);
// ISR_Register(CAN0TRX_IRQn, can_tx_handler);
//ISR_Register(CAN0ERR_IRQn, can_error_handler);
// ISR_DisRegister(CAN0REC_IRQn, can_recv_handler);
......
Firmware/Source/Device/Cmsemicon/BAT32A239/RTE/CAN/rte_can.h
View file @ f0d93af9
......@@ -11,8 +11,8 @@
#include "can.h"
typedef void (* can_rx_callback)(CanTxRxMsg*);
//typedef void (* can_rx_callback)(CanTxRxMsg*);
typedef uint8_t (* can_rx_callback)(CanTxRxMsg*);
typedef enum
{
CAN_500Kbps = 4,
......@@ -44,5 +44,5 @@ extern uint8_t rte_can_init(can_config_st_t *config);
extern uint8_t rte_can_deinit(CAN_CH ch);
extern uint8_t get_can_busoff(CAN_CH ch);
extern uint8_t reset_busoff(CAN_CH ch);
extern uint8_t Read_RingBuff(CanTxRxMsg *data);
#endif /* RTE_CAN_H_ */
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