-------------------------------------------------------------------------------
-- Module      = U2A_startup_PE0.850
-- Version     = E1.0.3g
-------------------------------------------------------------------------------
--                                  COPYRIGHT
-------------------------------------------------------------------------------
-- Copyright (c) 2018-2022 by Renesas Electronics Europe GmbH,
--               a company of the Renesas Electronics Corporation
-------------------------------------------------------------------------------
-- Purpose:      Startup Code
--
-------------------------------------------------------------------------------
--
-- Warranty Disclaimer
--
-- Because the Product(s) is licensed free of charge, there is no warranty
-- of any kind whatsoever and expressly disclaimed and excluded by Renesas,
-- either expressed or implied, including but not limited to those for
-- non-infringement of intellectual property, merchantability and/or
-- fitness for the particular purpose.
-- Renesas shall not have any obligation to maintain, service or provide bug
-- fixes for the supplied Product(s) and/or the Application.
--
-- Each User is solely responsible for determining the appropriateness of
-- using the Product(s) and assumes all risks associated with its exercise
-- of rights under this Agreement, including, but not limited to the risks
-- and costs of program errors, compliance with applicable laws, damage to
-- or loss of data, programs or equipment, and unavailability or
-- interruption of operations.
--
-- Limitation of Liability
--
-- In no event shall Renesas be liable to the User for any incidental,
-- consequential, indirect, or punitive damage (including but not limited
-- to lost profits) regardless of whether such liability is based on breach
-- of contract, tort, strict liability, breach of warranties, failure of
-- essential purpose or otherwise and even if advised of the possibility of
-- such damages. Renesas shall not be liable for any services or products
-- provided by third party vendors, developers or consultants identified or
-- referred to the User by Renesas in connection with the Product(s) and/or
-- the Application.
--
-------------------------------------------------------------------------------
-- Environment:
--              Device:         702Z19EDBG
--              IDE:            GHS Multi V7.1.4 or later
-------------------------------------------------------------------------------

-------------------------------------------------------------------------------
-- Revision Control History:
-- E1.0.0g :   13th-Feb-2018    : Initial Version
-- E1.0.1g :   25th-Jun-2019    : Support initial CRAM, LRAM for multi core
-- E1.0.2g :   09th-Jul-2019    : Performing Mutual Exclusion by Using the LDL
--                                and STC Instructions: .mev_address section
--                                in cRAM_0 is used for Sync flags because U2A
--                                doesn't have Mutual Exclusive Variable
--                                Register (G0MEVn)
-- E1.0.3g :   06th-Oct-2022    : Add CRAM0 initialization process
-------------------------------------------------------------------------------

  .set    CUx_EBV, 0x00038000
  .text

-------------------------------------------------------------------------------
------------- This ghs liability is used for sync between other core
-------------------------------------------------------------------------------
  .global ___ghs_board_devices_init
___ghs_board_devices_init:
  -- .mev_address section in cRAM_0 is used for Sync flags
  mov     ___ghsbegin_mev_address, r20
  st.w    r0, 0[r20]
  jmp     [lp]

-------------------------------------------------------------------------------
-------------- Sync PE0 Routine
-------------------------------------------------------------------------------
  .global _SYNC_PE0
_SYNC_PE0:
      mov     ___ghsbegin_mev_address, r20
      set1    1, 0x0[r20]
Lock: ldl.w   [r20], r21
      cmp     r0, r21
      bnz     Lock_wait
      mov     1, r21
      stc.w   r21, [r20]
      cmp     r0, r21
      bnz     Lock_success
Lock_wait:
      snooze
      br      Lock
Lock_success:
      jmp     [lp]

-------------------------------------------------------------------------------
-------------  PE0 Specific Startup Routine
-------------------------------------------------------------------------------
  .global _RESET_PE0
_RESET_PE0:
-------------  Memory Initialization
  -- Initialize Cluster Ram
  jarl  _Init_CRAM0, lp

  -- Initialize Cluster Ram
  jarl  _Init_CRAM1, lp

  -- Initialize Local Ram 0
  jarl  _Init_LRAM0, lp

#if defined (PE1_USED)
  -- Initialize Local Ram 1
  jarl  _Init_LRAM1, lp
#endif
#if defined (PE2_USED)
  -- Initialize Local Ram 2
  jarl  _Init_LRAM2, lp
#endif
#if defined (PE3_USED)
  -- Initialize Local Ram 3
  jarl  _Init_LRAM3, lp
#endif

-------------  PE0 Initialization
  -- Initialization of the global pointer
  mov   ___ghsbegin_sdabase, gp

  -- Initialization of the text pointer
  mov   __tp, r5

  -- Initialization of the stack pointer
  mov   ___ghsend_stack, sp

  -- Initialization of the interrupt base pointer
  mov   ___ghsbegin_inttable_PE0, r1
  ldsr  r1, INTBP, 1

  -- First set EBASE register address
  mov   __ex_entry_PE0, r10
  ldsr  r10, EBASE, 1

  -- then set 1 to PSW.EBV -> RBASE!=EBASE
  -- then set 1 to PSW.CU0 and CU1
  stsr  PSW, r10, 0
  mov   CUx_EBV, r11
  or    r11, r10
  ldsr  r10, PSW, 0

  -- Jump to the initialisation functions of the library
  -- and from there to main()
  jr    __start

-------------------------------------------------------------------------------
-------------  Init CRAM
-------------------------------------------------------------------------------
_Init_CRAM0:
  mov          0xAAAAAAAA, r6
  mov    ___ghs_cram0start, r7
  mov      ___ghs_cram0end, r8

_cram_loop:
  cmp                  r7, r8
  bne   2f
  1: jmp   [lp]
  2: st.w              r6, 0[r7]
     add                4, r7
     br               _cram_loop

_Init_CRAM1:
  mov          0xAAAAAAAA, r6
  mov    ___ghs_cram1start, r7
  mov      ___ghs_cram1end, r8

_cram_loop1:
  cmp                  r7, r8
  bne   2f
  1: jmp   [lp]
  2: st.w              r6, 0[r7]
     add                4, r7
     br               _cram_loop1

-------------------------------------------------------------------------------
-------------  Init LRAM 0
-------------------------------------------------------------------------------
_Init_LRAM0:
  mov         0xAAAAAAAA, r6
  mov    ___ghs_ramstart, r7
  mov      ___ghs_ramend, r8

_ram_loop:
  cmp                 r7, r8
  bne   2f
  1: jmp   [lp]
  2: st.w             r6, 0[r7]
     add               4, r7
     br               _ram_loop

-------------------------------------------------------------------------------
-------------  Init LRAM 1
#if defined (PE1_USED)
-------------------------------------------------------------------------------
_Init_LRAM1:
  mov         0xAAAAAAAA, r6
  mov   ___ghs_ram1start, r7
  mov     ___ghs_ram1end, r8

_ram_loop1:
  cmp                 r7, r8
  bne   2f
  1: jmp   [lp]
  2: st.w             r6, 0[r7]
     add               4, r7
     br               _ram_loop1
#endif

-------------------------------------------------------------------------------
-------------  Init LRAM 2
#if defined (PE2_USED)
-------------------------------------------------------------------------------
_Init_LRAM2:
  mov         0xAAAAAAAA, r6
  mov   ___ghs_ram2start, r7
  mov     ___ghs_ram2end, r8

_ram_loop2:
  cmp                 r7, r8
  bne   2f
  1: jmp   [lp]
  2: st.w             r6, 0[r7]
     add               4, r7
     br               _ram_loop2
#endif

-------------------------------------------------------------------------------
-------------  Init LRAM 3
#if defined (PE3_USED)
-------------------------------------------------------------------------------
_Init_LRAM3:
  mov         0xAAAAAAAA, r6
  mov   ___ghs_ram3start, r7
  mov     ___ghs_ram3end, r8

_ram_loop3:
  cmp                 r7, r8
  bne   2f
  1: jmp   [lp]
  2: st.w             r6, 0[r7]
     add               4, r7
     br               _ram_loop3
#endif


-------------------------------------------------------------------------------
-------------  Interrupt service routine of unused interrupts
-------------------------------------------------------------------------------
  .global  __unused_isr
__unused_isr:
  br    __unused_isr

-------------------------------------------------------------------------------
-------------  Start Section for exception table
.section".intvect_PE0",.text
-------------------------------------------------------------------------------
__ex_entry_PE0:

#if defined (PE0_USED)
----RESET
    .offset 0x0000
    .extern _RESET
    jr _RESET

----SYSERR
    .offset 0x0010
    .extern _SYSERR_PE0
    jr __unused_isr

----FETRAP
    .offset 0x0030
    .extern _FETRAP_PE0
    jr __unused_isr

----TRAP0
    .offset 0x0040
    .extern _EITRAP0_PE0
    jr __unused_isr

----TRAP1
    .offset 0x0050
    .extern _EITRAP1_PE0
    jr __unused_isr

----RIEX
    .offset 0x0060
    .extern _RIEX_PE0
    jr __unused_isr

----UCPOP
    .offset 0x0080
    .extern _UCPOP_PE0
    jr __unused_isr

----MIP_MDP
    .offset 0x0090
    .extern _MIP_MDP_PE0
    jr __unused_isr

----PIE
    .offset 0x00a0
    .extern _PIE_PE0
    jr __unused_isr

----MAE_MAEX
    .offset 0x00c0
    .extern _MAE_MAEX_PE0
    jr __unused_isr

----FENMI
    .offset 0x00e0
    .extern _FENMI_PE0
    jr __unused_isr

----FEINT
    .offset 0x00f0
    .extern _FEINT_PE0
    jr _FEINT_PE0

----EIINTn priority_0
    .offset 0x0100
    .extern _EINTPRIO_0_PE0
    jr __unused_isr

----EIINTn priority_1
    .offset 0x0110
    .extern _EINTPRIO_1_PE0
    jr __unused_isr

----EIINTn priority_2
    .offset 0x0120
    .extern _EINTPRIO_2_PE0
    jr __unused_isr

----EIINTn priority_3
    .offset 0x0130
    .extern _EINTPRIO_3_PE0
    jr __unused_isr

----EIINTn priority_4
    .offset 0x0140
    .extern _EINTPRIO_4_PE0
    jr __unused_isr

----EIINTn priority_5
    .offset 0x0150
    .extern _EINTPRIO_5_PE0
    jr __unused_isr

----EIINTn priority_6
    .offset 0x0160
    .extern _EINTPRIO_6_PE0
    jr __unused_isr

----EIINTn priority_7
    .offset 0x0170
    .extern _EINTPRIO_7_PE0
    jr __unused_isr

----EIINTn priority_8
    .offset 0x0180
    .extern _EINTPRIO_8_PE0
    jr __unused_isr

----EIINTn priority_9
    .offset 0x0190
    .extern _EINTPRIO_9_PE0
    jr __unused_isr

----EIINTn priority_10
    .offset 0x01a0
    .extern _EINTPRIO_10_PE0
    jr __unused_isr

----EIINTn priority_11
    .offset 0x01b0
    .extern _EINTPRIO_11_PE0
    jr __unused_isr

----EIINTn priority_12
    .offset 0x01c0
    .extern _EINTPRIO_12_PE0
    jr __unused_isr

----EIINTn priority_13
    .offset 0x01d0
    .extern _EINTPRIO_13_PE0
    jr __unused_isr

----EIINTn priority_14
    .offset 0x01e0
    .extern _EINTPRIO_14_PE0
    jr __unused_isr

----EIINTn priority_15
    .offset 0x01f0
    .extern _EINTPRIO_15_PE0
    jr __unused_isr

----EIINTn priority_16
    .offset 0x0200
    .extern _EINTPRIO_16_PE0
    jr __unused_isr

----EIINTn priority_17
    .offset 0x0210
    .extern _EINTPRIO_17_PE0
    jr __unused_isr

----EIINTn priority_18
    .offset 0x0220
    .extern _EINTPRIO_18_PE0
    jr __unused_isr

----EIINTn priority_19
    .offset 0x0230
    .extern _EINTPRIO_19_PE0
    jr __unused_isr

----EIINTn priority_20
    .offset 0x0240
    .extern _EINTPRIO_20_PE0
    jr __unused_isr

----EIINTn priority_21
    .offset 0x0250
    .extern _EINTPRIO_21_PE0
    jr __unused_isr

----EIINTn priority_22
    .offset 0x0260
    .extern _EINTPRIO_22_PE0
    jr __unused_isr

----EIINTn priority_23
    .offset 0x0270
    .extern _EINTPRIO_23_PE0
    jr __unused_isr

----EIINTn priority_24
    .offset 0x0280
    .extern _EINTPRIO_24_PE0
    jr __unused_isr

----EIINTn priority_25
    .offset 0x0290
    .extern _EINTPRIO_25_PE0
    jr __unused_isr

----EIINTn priority_26
    .offset 0x02a0
    .extern _EINTPRIO_26_PE0
    jr __unused_isr

----EIINTn priority_27
    .offset 0x02b0
    .extern _EINTPRIO_27_PE0
    jr __unused_isr

----EIINTn priority_28
    .offset 0x02c0
    .extern _EINTPRIO_28_PE0
    jr __unused_isr

----EIINTn priority_29
    .offset 0x02d0
    .extern _EINTPRIO_29_PE0
    jr __unused_isr

----EIINTn priority_30
    .offset 0x02e0
    .extern _EINTPRIO_30_PE0
    jr __unused_isr

----EIINTn priority_31
    .offset 0x02f0
    .extern _EINTPRIO_31_PE0
    jr __unused_isr

----EIINTn priority_32
    .offset 0x0300
    .extern _EINTPRIO_32_PE0
    jr __unused_isr

----EIINTn priority_33
    .offset 0x0310
    .extern _EINTPRIO_33_PE0
    jr __unused_isr

----EIINTn priority_34
    .offset 0x0320
    .extern _EINTPRIO_34_PE0
    jr __unused_isr

----EIINTn priority_35
    .offset 0x0330
    .extern _EINTPRIO_35_PE0
    jr __unused_isr

----EIINTn priority_36
    .offset 0x0340
    .extern _EINTPRIO_36_PE0
    jr __unused_isr

----EIINTn priority_37
    .offset 0x0350
    .extern _EINTPRIO_37_PE0
    jr __unused_isr

----EIINTn priority_38
    .offset 0x0360
    .extern _EINTPRIO_38_PE0
    jr __unused_isr

----EIINTn priority_39
    .offset 0x0370
    .extern _EINTPRIO_39_PE0
    jr __unused_isr

----EIINTn priority_40
    .offset 0x0380
    .extern _EINTPRIO_40_PE0
    jr __unused_isr

----EIINTn priority_41
    .offset 0x0390
    .extern _EINTPRIO_41_PE0
    jr __unused_isr

----EIINTn priority_42
    .offset 0x03a0
    .extern _EINTPRIO_42_PE0
    jr __unused_isr

----EIINTn priority_43
    .offset 0x03b0
    .extern _EINTPRIO_43_PE0
    jr __unused_isr

----EIINTn priority_44
    .offset 0x03c0
    .extern _EINTPRIO_44_PE0
    jr __unused_isr

----EIINTn priority_45
    .offset 0x03d0
    .extern _EINTPRIO_45_PE0
    jr __unused_isr

----EIINTn priority_46
    .offset 0x03e0
    .extern _EINTPRIO_46_PE0
    jr __unused_isr

----EIINTn priority_47
    .offset 0x03f0
    .extern _EINTPRIO_47_PE0
    jr __unused_isr

----EIINTn priority_48
    .offset 0x0400
    .extern _EINTPRIO_48_PE0
    jr __unused_isr

----EIINTn priority_49
    .offset 0x0410
    .extern _EINTPRIO_49_PE0
    jr __unused_isr

----EIINTn priority_50
    .offset 0x0420
    .extern _EINTPRIO_50_PE0
    jr __unused_isr

----EIINTn priority_51
    .offset 0x0430
    .extern _EINTPRIO_51_PE0
    jr __unused_isr

----EIINTn priority_52
    .offset 0x0440
    .extern _EINTPRIO_52_PE0
    jr __unused_isr

----EIINTn priority_53
    .offset 0x0450
    .extern _EINTPRIO_53_PE0
    jr __unused_isr

----EIINTn priority_54
    .offset 0x0460
    .extern _EINTPRIO_54_PE0
    jr __unused_isr

----EIINTn priority_55
    .offset 0x0470
    .extern _EINTPRIO_55_PE0
    jr __unused_isr

----EIINTn priority_56
    .offset 0x0480
    .extern _EINTPRIO_56_PE0
    jr __unused_isr

----EIINTn priority_57
    .offset 0x0490
    .extern _EINTPRIO_57_PE0
    jr __unused_isr

----EIINTn priority_58
    .offset 0x04a0
    .extern _EINTPRIO_58_PE0
    jr __unused_isr

----EIINTn priority_59
    .offset 0x04b0
    .extern _EINTPRIO_59_PE0
    jr __unused_isr

----EIINTn priority_60
    .offset 0x04c0
    .extern _EINTPRIO_60_PE0
    jr __unused_isr

----EIINTn priority_61
    .offset 0x04d0
    .extern _EINTPRIO_61_PE0
    jr __unused_isr

----EIINTn priority_62
    .offset 0x04e0
    .extern _EINTPRIO_62_PE0
    jr __unused_isr

----EIINTn priority_63
    .offset 0x04f0
    .extern _EINTPRIO_63_PE0
    jr __unused_isr

    .offset 0x0500

#endif
-------------  End of exception table
-------------------------------------------------------------------------------
